VLSI System Design (ECE-446)
Instructor: Prof. S. Mehdi Fakhraie


School of Electrical and Computer Engineering
University of Tehran
Fall 2006

 

News:

Day 13th: Final Project, a meeting about the final project will be held on Day 14th after the students presentation.

Day 9th: Some useful Tips (Assignment 6).

Azar 14th: An introductory presentation to LeonardoSpectrum 2005 and Synplify Pro 8.1 synthesis tools will be held on Wednesday (Azar 15th) at 15:00 (Class No. 12).

To get a local link of required tools to do computer assignments, please send an email to: a.farmahini [at] ece [dot] ut [dot] ac [dot] ir.

Course Description:

This is a second course in digital integrated system design with emphasis on physical implementation of digital systems in an ASIC environment. After a review of the historical developments and recent advancements, we will go over the critical parameters in VLSI system design. Next, we will consider process and layout related issues, design rule checking, circuit extraction from a VLSI layout, wiring, and interconnections problems related to deep submicron technologies. Then we will review how these concepts are put together in a CAD environment. An overview of different design methodologies and our design flow comes next. Although we will use SPICE for accurate estimation of the critical performance parameters of a circuit, emphasis is given to high-level and RTL design, modeling and simulation of digital systems, moving from an individualistic to a collective view of the digital world. This is complemented by going over Verilog RTL modeling of digital circuits, in contrast to our switch-level journey in that world in the Digital Integrated Circuits Course. A standard cell design methodology is pursued by describing the synthesis concept in modern digital design, covering power-optimized and physical synthesis. We will continue our look at system-level design by going over memories and their variations. Then, we will complete our study of some important arithmetic building blocks going over design and modeling of logarithmic-delay adders, multipliers and dividers. IO and clock-buffer design is considered next. These blocks are put together in a complex system by going over timing and signal integrity issues, covering static timing analysis, noise analysis, and power grid analysis. Finally, we will review test of digital circuits. Notice that static and dynamic combinational and sequential circuits are reviewed in the first month of the course by student seminars and collective studies outside the class reinforced by some quizzes.
The students will put their findings together by following weekly lab tutorials and assignments and delivering a final system level project with emphasis on team work.

Outline:

1) Historical review and recent developments
2) Processing, layout, and CMOS technology
3) Wiring and interconnects in deep submicron CMOS
4) Overview of CMOS combinational and sequential design
5) Implementation strategies for digital ICs
6) Verilog RTL modeling
7) Power-optimized and physical synthesis
8) Design hierarchy and database management.
9) Integrated memory systems.
10) Arithmetic and logic building blocks.
11) IO and clock buffer design.
12) Timing and signal integrity.
13) Multiple clock domain manipulation and synchronizers.
14) Digital system testing.

References:

1) Class notes and lab handouts.
2) Neil Weste and David Harris, CMOS VLSI Design, A Circuits and Systems Perspective, (3rd Edition),
Addison Wesley, 2005, ISBN: 0-321-14901-7.
3) Jan M. Rabaey, A. Chandrakasan, B. Nicolic, Digital Integrated Circuits, A Design Perspective. New Jersey: Prentice Hall, 2003.
4) Wai-Kai Chen, Editor-in-Chief, The VLSI Handbook. Florida: CRC Press, 2000.
5) Z. Navabi, Verilog Digital System Design, New York: McGraw-Hill, 1999.

Grading:

Class and computer assignments: 30%
Quizzes: 10%
Midterm: Students should prepare a poster presentation on one of the topics of interest to this class with instructor's confirmation, introduce it in a two-hour poster session to the class and instructor, and take part in a midterm exam from the poster
session material a week later: 20%
Final project (due Bahman 11th, 1385): 10%
Final exam: 30%