Address: School of Electrical and Computer Engineering, College of Engineering, University of Tehran, P.O.Box 14395-515, Tehran, Iran.

Office: Room 320

Phone: +98-21-6111-9748

Grad. Courses:

Methodologies and Algorithms for ESL Design Automation

Undergrad Courses:

Journal Papers:

• B. Alizadeh, and M. Fujita, Modular Data-path Optimization and Verification Based on Modular-HED, in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 9, September 2010, pages 1422-1435.
• B. Alizadeh, M. Mirzaei and M. Fujita, Coverage Driven High Level Test Generation using a Polynomial Model of Sequential Circuits, in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 5, May 2010, pages 737-748.
• O. Sarbishei, M. Tabandeh, B. Alizadeh and M. Fujita, A Formal Approach for Debugging Arithmetic Circuits, in IEEE Transactions on Computer-Aided-Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 5, May 2009, pages 742-754.
• B. Alizadeh and M. Fujita, A Unified Framework for Equivalence Verification of Datapath-oriented Applications, in IEICE TRANS. INF. & SYST., Vol. E92-D, No. 5, May 2009, pages 985-994.
• B. Alizadeh and Z. Navabi, Word Level Symbolic Simulation in Processor Verification, IEE Proceedings Computers and Digital Techniques Journal, Vol. 151, No. 5, September 2004, pages 356-366.
• B. Alizadeh and Z. Navabi, A New High Level Model to Check CTL Properties in VHDL Environment, Iranian Journal of Electrical and Computer Engineering, Vol. 1, No. 2, April 2003, pages 92-98.

 Conference/Symposium Papers:

• B. Alizadeh, A Formal Approach to Debug Polynomial Datapath Designs, ASP-DAC 2012 (to appear).
• B. Alizadeh, and M. Fujita, Early Case-splitting and False Path Detection to Improve High Level ATPG Techniques, ISCAS 2011, Brazil, pages 1463-1466.
• B. Alizadeh, and M. Fujita, Debugging and Optimizing High Performance Superscalar Out-of-Order Processors Using Formal Verification Techniques, ISQED 2011, USA, pages 1-6.
• B. Alizadeh, and M. Fujita, A Debugging Method for Repairing Post-Silicon Bugs of High Performance Processors in the Fields, ICFPT 2010, China, pages 328-331.
• M. Fujita, B. Alizadeh, H. Yoshida and T. Matsumoto, Post-silicon Debugging with High Level Design Descriptions and Programmable Controllers, MTV 2010, USA, pages 11-15.
• F. Haedicke, B. Alizadeh, G. Fey, M. Fujita, R. Drechsler, Polynomial datapath optimization using constraint solving and formal modeling, ICCAD 2010, USA, pages 756-761.
• B. Alizadeh, A.M. Gharehbaghi and M. Fujita, Pipelined Microprocessors Optimization and Debugging, ARC 2010, Thailand, pages 435-444.
• A.M. Gharehbaghi, B. Alizadeh and M. Fujita, Aggressive Over-clocking Support using a Novel Timing Error Recovery Technique on FPGAs, Symposium on FPGA 2010, USA.
• B. Alizadeh and M. Fujita, Guided Gate-level ATPG for Sequential Circuits using a High-level Test Generation Approach, ASP-DAC 2010, Taiwan, pages 425-430.
• B. Alizadeh and M. Fujita, Improved Heuristics for Finite Word-Length Polynomial Data-path Optimization, ICCAD 2009, USA, pages 169-174.
• B. Alizadeh and M. Fujita, Modular Arithmetic Decision Procedure with Auto-correction Mechanism, HLDVT 2009, USA, pages 138-145.
• B. Alizadeh and M. Fujita, Optimization of Modular Multiplication on FPGA using Don’t Care Conditions, ICFPT 2009, Australia, pages 399-402.
• B. Alizadeh and M. Fujita, Modularity in Word-level Decision Diagrams, RM 2009, Japan, pages 33-41.
• O. Sarbishei, B. Alizadeh and M. Fujita, Polynomial Data-path Optimization using Partitioning and Compensation Heuristics, DAC 2009, USA, pages 931-936.
• O. Sarbishei, B. Alizadeh and M. Fujita, A Debug Methodology for Arithmetic Circuits based on Horner Decision Diagrams, CFV 2009, France, pages 30-45.
• O. Sarbishei, M. Tabandeh, B. Alizadeh and M. Fujita, High-level Optimization of Integer Multipliers over a Finite Bit-width with Verification Capabilities, MEMOCODE 2009, USA, pages 56-65.
• B. Alizadeh and M. Fujita, Modular-HED: A Canonical Decision Diagram for Modular Equivalence Verification of Polynomial Functions, CFV 2008, Australia, pages 22-40.
• O. Sarbishei, B. Alizadeh and M. Fujita, Arithmetic Circuits Verification without Looking for Internal Equivalences, MEMOCODE 2008, USA, pages 7-16.
• B. Alizadeh and M. Fujita, Sequential Equivalence Checking using a Hybrid Boolean-Word Level Decision Diagram, CSICC 2008, Iran.
• M. Momtazpour, M. Tabandeh and B. Alizadeh, System-level Implementation of DSP Applications on FPGA, CSICC 2008, Iran.
• B. Alizadeh and M. Fujita, A Novel Formal Approach to Generate High-level Test Vectors without ILP and SAT Solvers, HLDVT 2007, USA, pages 97-104.
• B. Alizadeh and M. Fujita, A Hybrid Approach for Equivalence Checking between System Level and RTL Descriptions, IWLS 2007, USA, pages 298-304.
• B. Alizadeh and M. Fujita, LTED: A Canonical and Compact Hybrid Word-Boolean Representation as a Formal Model for Hardware/Software Co-designs, CFV 2007, Germany, pages 15-29.
• M. R. Saadat, M. Momtazpour and B. Alizadeh, Simulation and Improvement of Two Digital Adaptive Frequency Calibration Techniques for Fast Locking Wide-Band Frequency Synthesizers, DTIS 2007, pages 136-141.
• B. Alizadeh and M. Fujita, Automatic Merge-point Detection for Sequential Equivalence Checking of System-level and RTL Descriptions, Automated Technology for Validation and Analysis, Lecture Notes in Computer Science, Vol. 4762, November 2007, pages 129-144.
• B. Alizadeh, Word Level Functional Coverage Computation, ASP-DAC 2006, Japan, pages 7-12.
• A. Hooshmand, S. Shamshiri, M. Alisafaee, B. Alizadeh, P. Lotfikamran, M. Naderi and Z. Navabi, Binary Taylor Diagrams: An Efficient Implementation of Taylor Expansion Diagrams, ISCAS 2005, Japan, pages 424-427.
• B. Alizadeh and Z. Navabi, Using Integer Equations to Check PSL Properties in RT Level Design, IWSOC 2004, Canada, pages 83-86.
• B. Alizadeh and Z. Navabi, Symbolic Simulation Based on Integer Equations in Processor Verification, EDP 2004, USA, pages 202-209.
• B. Alizadeh and Z. Navabi, Property Checking Based on Hierarchical Integer Equations, ACSD 2004, Canada, pages 26-35.
• B. Alizadeh and M.R. Kakoee, Using Integer Equations for High Level Formal Verification Property Checking, ISQED 2003, USA, pages 69-74.
• B. Alizadeh, H.R. Hashempour and Z. Navabi, A VHDL Based Integrated Environment for Reliable System Design, NATW 1998, USA.
• B. Alizadeh, S.M. Fakhraei and Z. Navabi, Switch Level Simulation in VHDL, Computer Society Conference 1998, IRAN.
• B. Alizadeh and Z. Navabi, Component Modeling for Reliability by simulation, VIUF 1997, USA.