Ph.D in Computer Engineering, Sharif University of Technology, Tehran, Iran (2006-2010)

M.Sc in Computer Engineering, Sharif University of Technology, Tehran, Iran (2003-2005)

B.Sc in Computer Engineering, Amirkabir University of Technology, Tehran, Iran (1999-2003)

Dec. 2009-Sep. 2010: Visiting Ph.D. Student, PARSA Lab., Ecole Plytechnique Federale de Lausanne (EPFL), Lausanne, Switzerland

Sep. 2006- Now: Research Assistant, School of Computer Science, Institute for Studies in Fundamental Sciences (IPM), Tehran, Iran

Sep. 2006- Dec. 2010:  PhD Student, High-Performance Computer Architectures and Networks (HPCAN) Lab., Sharif University of Technology, Tehran, Iran

Grad:

M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, "Application-Aware Topology Reconfiguration for On-Chip Networks", in IEEE Transactions on Very Large Scale Integrated Circuits (IEEE TVLSI), Vol. 19, No. 11, Nov. 2011.

M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, "Virtual Point-to-Point Connections in NoCs", in IEEE Transactions on Computer-Aided Design for Integrated Circuits and Systems (IEEE TCAD), Vol. 29, No. 6, Jun. 2010.

M. Modarressi, H Sarbazi-Azad, "A High-Performance and Low-Power Reconfigurable Network-on-Chip Architecture", Chapter 13 in "Dynamic Reconfigurable Network-on-Chip Design: Innovations for Computational Processing and Communication", published by IGI Global Pubs, 2010.

R. Jabbarvand, M. Modarressi, H. Sarbazi-Azad, "A Reconfigurable Fault-Tolerant Routing Algorithm to Optimize the Network-on-Chip Performance and Latency in Presence of Intermittent and Permanent Faults", in The 29th. International Conference on Computer Design (ICCD'11), USA, Oct. 2011.

M. Asadinai, M. Modarressi, A. Tavakkol, H. Sarbazi-Azad, "Supporting Non-contiguous Processor Allocation in CMPs Using Virtual Point-to-point Links", in Design Automation and Test in Europe Conference (DATE'11), France, March 2011.

M. Modarressi, H. Sarbazi-Azad, A. Tavakkol, "An Efficient Dynamically Reconfigurable On-chip Network Architecture", in Design Automation conferecne (DAC'10), USA, June 2010.

M. Modarressi, H. Sarbazi-Azad, A. Tavakkol, "Low-power and High-Performance On-Chip Communication Using Virtual Point-to-Point Connections", in The IEEE/ACM International Symposium on Network-on-Chip (NoCS'09), USA, May 2009.

M. Modarressi, H. Sarbazi-Azad, M. Arjomand, "An SDM-Based Hybrid Packet-Circuit-Switched On-Chip Network", in Design, Automation, and Test in Europe Conference (DATE'09), France, Apr.2009.

R. Sabbaghi, M. Modarressi, H. Sarbazi-Azad, " The 2D DBM: An Attractive Alternative to the Simple 2D Mesh Topology for On-Chip Networks", in The 26th. International Conference on Computer Design (ICCD'08), USA, Oct. 2008.

M. Modarressi, H. Sarbazi-Azad, "Power-Aware Mapping for Reconfigurable NoC Architectures", in The 25th. International Conference on Computer Design (ICCD'07), USA, Oct. 2007. 

S. Hessabi, M. Modarressi, M. Goudarzi, H. Javan-Hemmat, "A Table-Based Application-Specific Prefetch Engine for Object-Oriented Embedded Systems", in International Conference on Embedded Computing Systems: Architectures, Modeling, and Simulation (IC-SAMOS VI), Greece, Jul. 2006.