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Saeed Safari
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| School of Electrical & Computer Engineering |
| Assistant Professor |
| Email: saeed [AT] ut.ac.ir |
| Personal Website: |
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| Education |
Ph.D.: Computer Engineering, CE Department, Sharif University of Technology in 2005.
M.Sc.: Computer Engineering, ECE Department, University of Tehran in 1998.
B.Sc.: Computer Engineering, CE Department, Sharif University of Technology in 1996.
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| Research Interests |
High-Level Synthesis
Test Synthesis
SOC Testing
Computer Arithmetic
Fault Tolerant Computing
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| Current Researches |
Soc Testing
Computer Arithmetic
Fault Tolerant Systems
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| Courses |
Computer Architecture
Computer Aided Design
Computer Arithmetic
Fault Tolerant Systems
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| Selected Publications |
1) S.Safari, A.H.Jahangir, H.Esmaeilzadeh,"A parameterized graph-based framework for high-level test synthesis" integration, the VLSI Journal, elsevier, to appear at 2006.
2) S.Safari, A.H. Jahangir, H.Esmaeilzadeh,"A novel model for behavioral test synthesis", the CSI Journal on computer, oct 2004, pp. 33-41(in persian)
3) S.Safari, A.H.Jahangir, "SOC test synthesis using test access mechanism design" ECTI-CON, Bangkok, Thailand, May 2005, pp.799-803.
4) S.Safari, H.Esmaeilzadeh, A.H.Jahangi, "Testability improvement during high-level synthesis". 12th Asian test symposium(ATS), nov.2003, p.505.
5) S.Safari, H.Esmaeilzadeh, A.H.Jahangir, "A novel improvement technique for high level test synthesis". IEEE International Symposium on Circuits and Systems(ISCAS), Bangkok, Thailand, 25-28 May 2003, pp.V609-V612.
6) S.Safari, H.Esmaeilzadeh, A.H.Jahangir, "A novel register allocation method for testability improvements", WRTLT, nov.2003, pp.96-102.
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