Ali Azarpeyvand

         

         PhD Candidate, Computer Architecture

         School of Electrical and Computer Engineering

         University of Tehran, 14395-1465, Iran

         Tel: +9821 88013196
         Fax: +9821 88633029
         Email: a.azarpeyvand@ece.ut.ac.ir

         Personal Homepage: www.znu.ac.ir

        Short Biography:

I was born in Zanjan Iran, in 1974. I received B.Sc. Degree in computer hardware from Sharif University of Technology, Tehran, Iran in 1997, and M.Sc. in Computer Engineering from the University of Tehran, Tehran, Iran in 2000. from July 1998 to August 2006 I was a senior digital design engineer in Emad Semicon Company and MERDCI. In September 2001 I have joined Zanjan University, Zanjan, Iran, as an instructor. Since Feb. 2007 I have been PhD condidate in ECE Department, University of Tehran.

   

        Education :

             Feb 2007 – now:   PhD candidate, Computer Architecture, University of Tehran, Tehran

             Sept. 1997 – March 2000:   M. Sc., Computer Architecture, University of Tehran, Tehran

                          Thesis Title:         Design and FPGA Implementation of a Paging Receiver Baseband Part Based on ERMES Standard

                        Advisor:              Prof. Mehdi Tavassoli Kilani, email: mtavassoli@valencesemi.com

                        Co-Advisor:         Prof. S. Mehdi Fakhraie, email: fakhraie@ut.ac.ir

             Sept. 1993 – Sept. 1997:   B. Sc., Computer Engineering, Sharif University of Technology, Tehran, Iran

                        Project Title:         Modeling of DLX RISC Processor in DataFlow Level of Abstraction

                       Advisor:               Prof. Shahin, Hessabi, email: Hessabi@ce.sharif.ac.ir

             1989 – 1993:   Diploma, Mathematics and Physics, Shariati High School., Zanjan

             Research Interests:

  • Reliable Computing in Nano Technology: Soft error

  • Asynchronous Design: Self-healing asynchronous circuits

  • Design, Verification and Test: Design for Verification, Online testing, Self-testing,

  • Embedded Systems: Embedded Processors, HW/SW Co-Design

  • Computer Architecture: Parallel architecture

    •

                 Research and Work Experience:

                 2005 – Now: Research Assistant, Silicon Intelligence Lab., School of ECE, University of Tehran, Iran.

    • Reliable computing

    • Self-healing asynchronous circuits with fault location

               Publications:

                   Journal paper(s)

    1) Amir M. Sodagar, G. R. Lahiji AND Ali Azarpeyvand, “Reduced-Memory Direct Digital Frequency Synthesizer Using Parabolic Initial Guess”, Kluwer Academic Journal of Analog Integrated Circuits and Systems, pp 89-96, vol 34, February 2003.

                   Conference paper(s)

    1) A.M. Sodagar, G.R. Lahiji, and A. Azarpeyvand, “A Novel Architecture For Sine-Output Direct Digital Frequency Synthesizers Using Parabolic Approximation”, IEEE International Conference on Electronics, Circuits, & Systems (ICECS’2k), pp 256-259, Lebanon.

    2) R. Tusi, A. Azarpeyvand, and M.T. Kilani, “A Programmable BCH Decoder for Radio Paging Receivers: VHDL Design and FPGA Implementation”, Proceeding of 5 Annual International CSI Computer Conference, pp 35-38, March 2000.

                  Presentations:

                     Local:

                        1) Fully Digital FSK Demodulator for paging application

                        2) Self-Healing Asynchronous circuits

                        3) Functional Verification