Abbas Banaiyan Mofrad

         

         M.Sc. Graduate, Computer Architecture

         School of Electrical and Computer Engineering

         University of Tehran, Tehran 14395-515, Iran

         Cell: +98912 6971751
         Tel: +9821 88013196
         Fax: +9821 88633029
         Email: a.banaiyan@ece.ut.ac.ir

 

Short Biography:

I received my BSc degree in computer engineering from Isfahan University of Technology, Isfahan, Iran in 2002 and my MSc degree in computer architecture from University of Tehran, Tehran, Iran in 2006. My research interests include Computer Architecture, Fuzzy Systems, VLSI design and test, and High-level Synthesis.

Education :

2003 – 2006:   M. Sc., Computer Architecture, University of Tehran, Tehran, Iran

Thesis Title:         Customized Functions and Processor for Fuzzy System

Advisor:              Prof. S. Mehdi Fakhraie, email: fakhraie@ut.ac.ir

1998 – 2003:   B. Sc., Computer Engineering, Isfahan University of Technology, Isfahan, Iran 

Project Title:         Design of User Management System of a Digital Library

Advisor:               Prof. F. Hendessi, email: hendesi@cc.iut.ac.ir

1994 – 1998:   Diploma, Mathematics and Physics, Shahid Ezhehi High School (NODET), Isfahan, Iran

Research Interests:

  • Fuzzy Systems : Fuzzy Processors, Hardware implementation of fuzzy systems 

  • Computer Architecture : DSP Processors, High-performance architectures

  • VLSI Design : NoC/SoC design, Low power architectures

  • Design, Verification and Test : NoC testing, Design for test

  • Embedded Systems: Embedded processors, HW/SW co-design 

  • High-level Synthesis : GA-based High-level Synthesis, NoC synthesis

    •

    Research and Work Experience:

    2001 – 2003: Eastern Information Technology Co., ICT Park, Isfahan University of Technology, Isfahan, Iran.

    Publications:

    Journal paper(s)

    1. A. Banaiyan, H. R. Mahdiani, and S. M. Fakhraie, “New Defuzzification Techniques for Efficient Hardware and Software Implementation issues,” submitted to IEEE Transactions on Systems, Man, and Cybernetics.

    Conference paper(s)

    1. 1. M. E. Salehi, S. M. Fakhraie, A. Banaiyan , and A. Hormati, “Design of a Custom Packet Switching Engine for Network Applications,” in Proc. of the 13th International CSI Computer Conference (CSICC’08), Kish island, Iran, Mar. 2008.
    2. E. Salehi, A. Hormati, A. Banaiyan, and S. M. Fakhraie, “A proposed architecture for layer-2 packet processor,” in Proc. of the 15th Iranian Conference on Electrical Engineering (ICEE’07), Tehran, Iran, May 2007.
    3. H. R. Mahdiani, A. Banaiyan , and S. M. Fakhraie, “Hardware implementation and comparison of new defuzzification methods in fuzzy processors,” IEEE ISCAS 2006, Island of Kos, Greece, pp. 4619-4622, May 2006 [download].
    4. A. Banaiyan , H. R. Mahdiani, and S. M. Fakhraie, “Software implementation issues of existing and new defuzzification methods, ” FUZZ-IEEE 2006, Vancouver, Canada, pp. 8476-848, July 2006 [download].
    5. A. Banaiyan , H. R. Mahdiani, and S. M. Fakhraie, “PiFie: A Platform-Independent Fuzzy Instruction Set Extension, ” NAFIPS 2006, Montral, Canada, June 2006 [download].
    6. A. Banaiyan , M. Salmani Jelodar, and S. M. Fakhraie, “ISA Extension to General Purpose Processors for Fuzzy and Genetic Algorithm Applications,” NAFIPS 2006, Montreal, Canada, June 2006 [download].
    7. M. Hosseinabady, A. Banaiyan , M. N. Bojnordi, and Z. Navabi, “A concurrent testing method for NoC switches, ” IEEE DATE 2006, Munich, Germany, pp. 1171-1176, 2006 [download].
    8. M. Hossenabady, M. N. Bojnordi, A. Banaiyan , and Z. Navabi, “An efficient online BIST architecture for NoCs, ” ETS 2006, London, UK, in press [download].
    9. A. Banaiyan , H. Esmaeilzadeh, and S. Safari, “Co-Evolution Scheduling and Mapping for High-Level Synthesis, ” IEEE ICEIS 2006, Islamabad, Pakistan, pp. 269-273, Apr. 2006 [download].
    10. A. Banaiyan , H. R. Mahdiani, and S. M. Fakhraie, “Cost-performance co-analysis in VLSI implementation of existing and new defuzzification methods,” in Proc. Int. Conf. Computational Intelligence for Modeling, Control and Automation, Vienna, Austria, pp. 828-833, Dec. 2005 [download].
    11. M. N. Bojnordi, M. Semsarzadeh, A. Banaiyan , and A. Afzali-Kusha, “A simple low-cast and low-power switch architecture,” in Proc. Int. Conf. Microelectronics, Taxila, Pakistan, pp. 194-197, Dec. 2005 [download].

    Presentations:

    Oral:

    1. A. Banaiyan, H. R. Mahdiani, and S. M. Fakhraie, “Cost-performance co-analysis in VLSI implementation of existing and new defuzzification methods,” in Proc. Int. Conf. Computational Intelligence for Modeling, Control and Automation, Vienna, Austria, Dec. 2005.

    Thesis Abstract:

    Considering new requirements and applications developed recently in the field of fuzzy logic, implementation of high speed fuzzy systems with high computational power is one of the main issues that many activities are performed around it. In this project, after review of fuzzy algorithms and systems, some proper solutions are proposed to improve the performance and speed of execution of fuzzy applications using different hardware and software platforms. Defuzzification is one of the main sections of each fuzzy system and actually is the most complex one of them. Therefore, its optimization has a great effect on system efficiency. First, three new defuzzification methods are introduced which are more appropriate for implementation. These methods are realized by simple structures that have high output accuracy and can be both hardware and software implemented in multiple hardware structures and platforms. In the next section of this thesis, to increase the speed of fuzzy applications execution on general purpose processors, after complete study and survey of different fuzzy systems and their involved functions and operators, fuzzy packages and fuzzy system design toolboxes, a complete, simple, general, platform-independent, efficient and fuzzy application-specific instruction set is proposed. Then, hardware blocks for each of such instructions and also a reconfigurable hardware which can execute most of them, are designed and implemented. Also, these fuzzy-specific instructions are extended to data path and instruction set of a general purpose processor (LEON2), and its efficiency is evaluated. Finally, a new pipeline fuzzy processor by a scalable and flexible structure is developed. In design of its pipeline and functional units, achieving the maximum execution speed is our objective. First, each functional unit of this processor is designed and implemented, and then by integrating them under an efficient pipeline, the final structure of the processor is created. In this thesis, different tables and graphs are produced that demonstrate various tradeoffs in fuzzy system design. Based upon the provided information, system designers can make quantitative decision in realization of their applications.