Amin Farmahini-Farahani

         

         M.Sc., Computer Engineering – Architecture Design

         School of Electrical and Computer Engineering

         University of Tehran, Tehran 14395-1465, Iran

         Tel (SILab at UT): +9821 88013196 (Leave your message)
         Email:

         CV [PDF]
        


Short Biography           

Amin Farmahini-Farahani was born in 1983 in Tehran, Iran. He received the B.Sc. degree in Computer Engineering in 2005 as a top student from the Iran University of Science and Technology, Tehran, Iran. From Sep. 2005 to Feb. 2008, He was an M.Sc. student of Computer Architecture at the University of Tehran, Tehran, Iran. He was a research assistant in both School of ECE, University of Tehran and Computer Engineering Dep., Iran University of Science and Technology. He has worked on design and implementation of hardware engines for bio-inspired algorithms under the supervision of Dr. Sied Mehdi Fakhraie and Dr. Saeed Safari. His research interests include reconfigurable computing, bio-inspired computing, on-chip multiprocessing, parallel architectures, computer aided design, HW/SW codesign, and application specific hardware cores. He is currently a student member of IEEE.
 

Education          

             2005 – 2008:   M.Sc., Computer Engineering, University of Tehran (UT), Tehran, Iran.

                          Thesis Title:         Design and Implementation of Bio-Inspired Hardware Cores [PDF (Persian)], [PPT (English)], [Abstract (English)]

                        Advisor:              Dr. S. Mehdi Fakhraie, Associate Prof., email: fakhraie@ut.ac.ir

                        Co-Advisor:         Dr. S. Safari, Assistant Prof., email: saeed@ut.ac.ir

             2001 – 2005:   B.Sc., Computer Engineering, Iran University of Science and Technology, Tehran, Iran.

                        Project Title:        Combinational Circuits Design using Genetic Algorithm

                       Advisor:               Dr. M. R. Jahed-Motlagh, Assistant Professor, email: jahedmr@iust.ac.ir

             2000 – 2001:   Pre University, Mathematics and Physics, Shahid Motahhari Pre Univ., Tehran, Iran.

             1997 – 2000:   Diploma, Mathematics and Physics, Alborz High School, Tehran, Iran.


Research Interests

  • Reconfigurable Computing

  • Bio-Inspired and Intelligent Computing

  • System-On-a-Chip (SOC) Design and On-Chip Multiprocessing (CMP)

  • Parallel Hardware Architectures

  • Computer Aided Design (CAD)

  • FPGA/ASIC Design

  • HW/SW Codesign and Embedded Systems Design

  • Application Specific Hardware Cores


  • Research and Work Experiences

    Sep. 2005 – Feb. 2008: Research Assistant, Silicon Intelligence Lab., School of ECE, University of Tehran, Tehran, Iran.

    May 2006 – Mar. 2008: Research Assistant, Research Institute of Advanced Technologies in Automotive Industry, Tehran, Iran.

    Fall 2004 – June 2008: Teaching Assistant, Digital Logic Circuits, Computer Eng. Dep., Iran University of Science and Technology, Tehran, Iran.

    Spring and Summer 2007: Instructor of Digital Logic Circuits Lab., Computer Eng. Dep., Iran University of Science and Technology, Tehran, Iran.

    Fall 2006: Teaching Assistant, VLSI System Design, School of ECE, University of Tehran, Iran.

    Fall 2006: Teaching Assistant, Advanced VLSI, School of ECE, University of Tehran, Iran.

    2005 – 2006: Teaching Assistant, Computer Architecture, University of Science and Technology, Tehran, Iran.

    June 2003 June 2005: Research Assistant, Information Technology Research Center (ITRC), Computer Eng. Dep., Iran University of Science and Technology, Tehran, Iran.

    Summer 2004: Intern, Microelectronic Research and Development Center of Iran (MERDCI), Tehran, Iran.


            Publications

       Journal Paper

    1. M. Ghaffari-Miab, A. Farmahini-Farahani, R Faraji-Dana, and C. Lucas, “An Efficient Hybrid Swarm Intelligence-Gradient Optimization Method for Complex Time Green's Functions of Multilayer Media,” Progress In Electromagnetics Research (PIER), vol. 77, pp. 181-192, 2007.

       Conference Papers

    1. A. Farmahini-Farahani, S. M. Fakhraie, and S. Safari, “Scalable Architecture for on-Chip Neural Network Training using Swarm Intelligence,” in Proc. of the Design, Automation and Test in Europe Conf. (DATE’08), Munich, Germany, Mar. 2008, pp. 1340-1345.
       

    2. A. Farmahini-Farahani, S. M. Fakhraie, and S. Safari, “SOPC-Based Architecture for Discrete Particle Swarm Optimization,” in Proc. IEEE Intl. Conf. on Electronics, Circuits and Systems, Marrakech, Morocco, Dec. 2007, pp. 1003-1006.
       

    3. N. Sedaghati-Mokhtari, M. N. Bojnordi, A. Farmahini-Farahani, M. Mousavinezhad, and S. M. Fakhraie, “Simulation of Voice Processing Applications through VLIW DSP Architectures,” in Proc. IEEE Intl. Conf. on Electronics, Circuits and Systems (ICECS), Marrakech, Morocco, Dec. 2007, pp. 291-293.
       

    4. A. Farmahini-Farahani, M. Laali, A. Moghimi, S. M. Fakhraie, and S. Safari, “Mesh Architecture for Hardware Implementation of Particle Swarm Optimization,” in Proc. IEEE Intl. Conf. on Intelligent & Advanced Systems, Kuala Lumpur, Malaysia, Nov. 2007.
       

    5. A. Naghdinezhad, A. Farmahini-Farahani, M. R. Hashemi, and O. Fatemi, “An Adaptive Unequal Error Protection Method for Error Resilient Scalable Video Coding Using Particle Swarm,” in Proc. IEEE Intl. Conf. on Signal Processing and Communication, Dubai, UAE, Nov. 2007, pp. 396-399.
       

    6. H. Assasi, A. Farmahini-Farahani, M. Hamzeh, S. Mohammadi, and C. Lucas, “Input Stimuli Evolution for RFID Tag Functional Verification,” in Proc.
      Intl. Conf. on RFID Eurasia
      , Istanbul, Turkey, Sep. 2007, pp. 1-6.

       

    7. A. Farmahini-Farahani, M. Kamal, S. M. Fakhraie, and S. Safari, “HW/SW Partitioning using Discrete Particle Swarm,” in Proc. ACM Great Lakes Symp. on VLSI, Stresa-Lago Maggiore, Italy, Mar. 2007, pp. 359-364.
       

    8. A. Farmahini-Farahani and S. M. Fakhraie, “SOPC-Based Particle Swarm Optimization,” in Proc. Intl. CSI Computer Conf., Tehran, Iran, Feb. 2007, pp. 1536-1541.
       

    9. M. H. Neishabouri, M. Hamzeh, A. Farmahini-Farahani, P. Saeedi, M. Daneshtalab, and N. Yazdani, “Voltage Scheduling Technique during System Level Design Using UML-RT Model,” in Proc. IEEE Design and Test Workshop, Dubai, UAE, Nov. 2006.
       

    10. P. Saeedi, A. Farmahini-Farahani, M. Hamzeh, M. H. Neishabouri, and A. Afzali-Kusha, “Network-On-Chip Thermal-Balanced Mapping,” in Proc. IEEE Design and Test Workshop, Dubai, UAE, Nov. 2006.
       

    11. A. Farmahini-Farahani, M. Kamal, and M. Salmani-Jelodar, “Parallel-Genetic-Algorithm-Based HW/SW Partitioning,” in Proc. Intl. Symp. Parallel Computing in Electrical Engineering, Poland, Sep. 2006, pp. 337-342.
       

    12. M. Kamal, A. Farmahini-Farahani, and M. Salmani-Jelodar, “Automatic Combinational Circuit Design using Genetic Algorithm,” in Proc. Conf. Intelligent Systems, Tehran, Iran, 2005 (Persian).

    * Papers available upon request


    Last update: June 20 2008.