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Fatemeh Kashfi
M.Sc. Candidate, Electronics (Circuit and System) School of Electrical and Computer Engineering University of Tehran, 14395-1465, Iran
Tel: +9821 88013196
CV: [download] |
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Short Biography:
I was born in Shiraz, Iran in 1983. I received my BS in Electrical Engineering from University of Tehran, Tehran, Iran, in 2005. I am currently working toward the M. Sc. degree in Electronics (Circuit and System) at University of Tehran. My thesis is based on very high speed digital circuit implementation. My research interests also include process variations, yield, and soft errors.
Education :
Research Interests:
Very High Speed Digital Integrated Circuit Design
Low Power Digital Integrated Circuit Design
Process Variations and Soft Error
Computational and Arithmetic Blocks
RF Digital Blocks
Research and Work Experience:
Sep 2005 – Now
Research Assistant – Silicon Intelligence Lab (University of Tehran)
Design of very high speed (Giga Hertz Clock Frequency) adders, multipliers, and MACs in 65nm CMOS technology
Process Variations deep studying
Design of Process Variations detector circuits
Soft Error deep studying
Design and Implementation of a Digital RF Processor blocks (All Digital PLL and RF Transmitter)
Sep 2005 – Sep 2006
Research Assistant – Analog IC Lab (University of Tehran)
Design and Simulation of a low power 12bit 100Msps pipeline ADC in 3.3V and 0.35um CMOS process.
Design and simulation of a Gm-C filter.
Oct 2003 – Sep 2004
Research Assistant –VLSI Lab (University of Tehran)
Deep Studying on Interconnect Crosstalk, classifying, finding the effective parameters and ways to reduce this noise, and simulating some models
Studying the hardware and programming language of ST7 microcontrollers and designing of several circuits with them for a biomedical engineering application.
Jan. 2006- Feb 2007
Working in Sina Microelectronics Inc.
Designing a PCI based Linecard board with 4 FXSs and 2 FXOs for IP PBX application. The design also included manual place and route; CPLD programming, synthesis and implementation; and driver design.
Teaching Experience
Spring 2006
Teaching Assistant, University of Tehran, Digital Electronics, Instructor: Prof. S. Mehdi Fakhraie
Fall 2007
Teaching Assistant, University of Tehran, VLSI, Instructor: Prof. S. Mehdi Fakhraie
Fall 2007
Teaching Assistant, University of Tehran, Advanced VLSI, Instructor: Prof. S. Mehdi Fakhraie
Spring 2007
Teaching Assistant, University of Tehran, Digital Electronics, Instructor: Prof. S. Mehdi Fakhraie
Publications:
Journal paper(s)
- F. Kashfi, A. Agah, S. Mehdi Fakhraie, and S.Safari “15GHz Carrylook-Ahead Low-Voltage-Swing Adder,” IEICE Electronics Express, vol. 4, no. 22, pp 696-700, (2007) [download].
Conference paper(s)
- F. Kashfi, and S. Mehdi Fakhraie, “Implementation of a high-speed low-power 32-bit adder in 70nm technology,” IEEE ISCAS’06, Greece, May 2006 [download].
- F. Kashfi, and N. Masoumi, “Optimization of speed and power in a 16-bit carry skip adder in 70nm technology,” IEEE MESCAS’06, Porto Rico, Aug. 2006 [download].
Presentations:
Oral:
F. Kashfi, and S. M. Fakhraie, “Implementation of a high-speed low-power 32-bit adder in 70nm technology,” IEEE ISCAS’06, Greece, May 2006 [download].
Thesis Abstract:
CMOS technology has reached to Nano scales. Transistors and circuits has encountered many expected and unexpected problems, some issues like Process Variations, Soft Errors, yield and leakages. New circuit design needs to consider these problems. In my thesis besides deep study on Process Variations, Soft Errors, and power leakages I am working on designing and implementation of very high speed computational digital circuits in Sub-70nm CMOS technology. This design will consider Nano-CMOS main issues like process variations, and power leakages.