Mohammad Alisafaee

         

         Research Assistant

         School of Electrical and Computer Engineering

         University of Tehran, 14395-515, Iran

         Tel: +9821 61114341
         Fax: +9821 88633029
         Email: alisafaee@cad.ece.ut.ac.ir

         Personal Homepage: http://cad.ece.ut.ac.ir/~alisafaee

Short Biography:

Mohammad Alisafaee is a research assistant at University of Tehran, Iran.  He received a BS degree in electrical and computer engineering from the University of Tehran, Tehran, Iran, in 2002, and a master's degree in computer architecture from University of Tehran in 2005.  His research interests includes parallel computer architecture, network processors, embedded systems and on-line testing of digital systems.

Education :

2002 – 2005:   M. Sc., Computer Architecture, University of Tehran, Tehran

Thesis Title:         Optimum Design of Memory Management Processors

Advisor:              Prof. S. Mehdi Fakhraie, email: fakhraie@ut.ac.ir

Consultant:          Prof. Zainalabedin Navabi, email: navabi@ece.neu.edu

1998 – 2002:   B. Sc., Electrical and Computer Engineering, University of Tehran, Tehran

Project Title:         Test Set Evaluation Automation

Advisor:                Prof. Zainalabedin Navabi, email: navabi@ece.neu.edu

1994 – 1998:   Diploma, Mathematics and Physics, Allameh High School, Tehran

Research Interests:

  • Computer Architecture: Parallel and Networked Architectures

  • Design, Verification and Test: Online testing, Self-testing, Memory testing

  • Embedded Systems: Embedded Processors, HW/SW Co-Design

  • Network Systems: Network Processors, Network Buffers

    •

    Research and Work Experience:

                       2005 – Now: Research Assistant, Silicon Intelligence Lab., School of ECE, University of Tehran, Iran.

  • Contributing to the SoPC realization of high-performance memory controllers for embedded network applications.

    •

                       2003 – Now: Research Assistant, CAD Lab., School of ECE, University of Tehran, Iran.

  • Contributing to the SoPC realization of high-performance memory controllers for embedded network applications.

  • Working as head engineer in the design and implementation of a network processor for IP/MPLS switches.

  • Contributing to the design of on-line and off-line test schemes for VLSI circuits.

    •

                       2003 – 2004: Research Assistant, Multimedia Lab., School of ECE, University of Tehran, Iran.

  • Design and SoPC implementation of an MP3 decoder.

    • Publications:

    Conference paper(s)

    1. M. Alisafaee, Sh. Ataee, S. M. Fakhraie, “Bandwidth-Enhanced Waste-Free Control Technique for Multi-Queue Network Buffers,” in Proceeding of International Symposium on Telecommunication (IST2005), pp. 513-516, Shiraz, Iran, September 2005. [download]
    1. M. Alisafaee, and S. M. Fakhraie, “Architecture of an Embedded Queue Management Engine for High-Speed Network Devices,” in Proceeding of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2005), pp. 1907-1910, Cincinnati, Ohio, August 2005. [download]
    1. M. Alisafaee, and S. M. Fakhraie, "Design and Implementation of a Bandwidth-Enhanced Packet Buffer," in Proceeding of Iranian Conference on Electrical Engineering (ICEE2005) pp. 1907-1910, Zanjan, Iran, May 2005. [download]
    1. S. Hatami, M. Alisafaee, E. Atoofian, Z. Navabi, and A. Afzali-Kusha, “A Low-Power Scan-Path Architecture,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS2005), pp. 5278-5281, Kobe, Japan, May 2005.
    1. Hooshmand, S. Shamshiri, M. Alisafaee, B. Alizadeh, P. Lotfikamran, M. Naderi, and Z. Navabi, “Binary Taylor Diagrams (BTD): An Efficient Way of Implementing Taylor Expansion Diagrams,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS2005), pp. 424-427, Kobe, Japan, May 2005.
    1. M. Alisafaee, Z. Navabi and S. M. Fakhraie, “Doubling Memory Bandwidth for Single-Queue Network Buffers Using Uniform Distribution Method,” in Proceedings of International Conference of Computer Society of Iran, pp. 172-179, Tehran, Iran, February 2005. [download]
    1. M. Alisafaee, S. Hatami, E. Atoofian, Z. Navabi, and A. Afzali-Kusha,, “Architecture of a Data Compression-Based Low-Power Scan-Path,” in Proceedings of IEEE International Conference on Microelectronics (ICM2004), Tunisia, December 2004.
    1. M. Alisafaee, P. Lotfikamran, S. Shamshiri, H. Esmaeilzadeh, A. Pedram, and Z. Navabi, “MCBIST: A New On-line BIST Scheme,” in Proceedings of IEEE Workshop on RTL and High Level Testing (WRTLT04), Osaka, Japan, 2004.
    1. S. Shamshiri, H. Esmaeilzadeh, M. Alisafaee, P. Lotfikamran and Z. Navabi, “Test Instruction Set (TIS): An Instruction Level CPU Core Self-Testing Method,” in Proceedings of IEEE European Test Symposium (ETS04), pp. 15-16, Corsica, France, May 2004.
    1. Hooshmand, S. Shamshiri, M. Alisafaee, B. Alizadeh, P. Lotfikamran, M. Naderi, P. Riahi and Z. Navabi, “Binary Taylor Diagrams (BTD): An Efficient Way of Implementing Taylor Expansion Diagrams,” in Proceedings of IEEE North Atlantic Test Workshop, pp. 7-13, VT, USA, May 2004.
    1. E. Atoofian, S. Hatami, Z. Navabi, M. Alisafaee, and A. Afzali-Kusha, “A New Low-Power Scan-Path Architecture,” in Proceedings of IEEE Workshop on RTL and High Level Testing (WRTLT03), pp. 91-95, Xi’an, China, November 2003.

    Presentations:

                      Oral:

    1. E. Atoofian, S. Hatami, Z. Navabi, M. Alisafaee, and A. Afzali-Kusha, “A New Low-Power Scan-Path Architecture,” IEEE Workshop on RTL and High Level Testing (WRTLT03), Xi’an, China, November 2003.

    2. M. Alisafaee, Sh. Ataee, S. M. Fakhraie, “Bandwidth-Enhanced Waste-Free Control Technique for Multi-Queue Network Buffers,” International Symposium on Telecommunication (IST2005), pp. 513-516, Shiraz, Iran, September 2005 [download]

    3. M. Alisafaee, and S. M. Fakhraie, “Architecture of an Embedded Queue Management Engine for High-Speed Network Devices,” IEEE International Midwest Symposium on Circuits and Systems (MWSCAS2005), Cincinnati, Ohio, August 2005. [download]

    4. M. Alisafaee, and S. M. Fakhraie, "Design and Implementation of a Bandwidth-Enhanced Packet Buffer," Iranian Conference on Electrical Engineering (ICEE2005) , Zanjan, Iran, May 2005. [download]

    5. M. Alisafaee, Z. Navabi and S. M. Fakhraie, “Doubling Memory Bandwidth for Single-Queue Network Buffers Using Uniform Distribution Method,” International Conference of Computer Society of Iran, Tehran, Iran, February 2005. [download]