Sied Mehdi Fakhraie Associate Professor, and Associate Dean for Research University College of Engineering University of Tehran North Kargar Ave., Tehran, 14395-515, Iran   Phone: (+98-21) 6111 4340 (Office) FAX: (+98-21) 8802 9354 E-mail: fakhraie@ut.ac.ir
	Silicon Intelligence Lab

Short Biography:

Sied Mehdi Fakhraie was born in Dezfoul, Iran, in 1960. He received his M.Sc. degree in electronics from the University of Tehran, Tehran, Iran, in 1989 an the Ph.D. degree in electrical and computer engineering from the University of Toronto, Toronto, ON, Canada in 1995. Since 1995, he has been with the School of Electrical and Computer Engineering, University of Tehran, where he is now an Associate Professor. He has been the founder of the VLSI Circuits and Systems Laboratory and is now Director of Silicon Intelligence and VLSI Signal Processing Laboratory. From September 2000 to April 2003, he was with Valence Semiconductor Inc. and has worked in Dubai, UAE, and Markham, Canada offices of Valence as Director of ASIC/SoC Design and also technical lead of Integrated Broadband Gateway and Family Radio System baseband processors.
During the summers of 1998, 1999, and 2000, he was a visiting professor at the University of Toronto, where he continued his work on efficient implementation of artificial neural networks. He is coauthor of the book VLSI-Compatible Implementation of Artificial Neural Networks (Boston, MA: Kluwer, 1997). He has also published more than 70 reviewed conference and journal papers. He has worked on many industrial IC design projects including design of network processors and home gateway access devices, DSL modems, pagers, and one- and two-way wireless messaging systems, and digital signal processors for personal and mobile communication devices. His research interests include system design and ASIC implementation of integrated systems, novel techniques for high-speed digital circuit design, and system-integration and efficient VLSI implementation of intelligent systems.

Education :

Ph.D.

Electrical and Computer Engineering from the University of Toronto, Toronto, Canada, June 1995.
Thesis: VLSI-Compatible Implementations of Artificial Neural Networks.

M.Sc.

Electrical Engineering-Electronics from the University of Tehran, Iran, Feb. 1989.
Thesis: Real-Time Solution of Nonlinear Programming Problems by Analog Hardware and Neural Computers.

B.Sc.

Thesis: Iterative Fourier-Domain Solution of the Radiation Equation for a 2-D Microstrip Antenna.

Professional Experiences:

• Associate Dean for Research: University College of Engineering, University of  Tehran, from Sep. 2006-present.

• Associate Chair for Graduate Studies: School of Electrical and Computer Engineering, University of  Tehran, from Sep. 2004-Aug. 2006.

• Associate Professor: Department of Electrical and Computer Engineering, University of  Tehran. Taught graduate courses in advanced VLSI design, Custom Implementation of DSP Systems, and Parallel Processing. Courses taught include undergraduate Digital Electronics, and VLSI System Design. July 2004-present.

• Director of Silicon Intelligence and VLSI Signal Processing Laboratory, the University of Tehran: Most-recent research included: Design and SoC/SoPC implementation of accelerating engines for execution of genetic, fuzzy, and neural algorithms, bit-true modeling and VLSI design of the DSP and MAC parts of wireless communication protocols including WiMAX (802.16), VoIP over WiFi (802.11), UWB, DAB, and Zigbee, and low-power and high-speed novel logic styles. Sep. 2004- present.

• Director, ASIC/SOC Design, Valence Semiconductor Inc., Toronto, Canada: Technical supervision of a team of system and ASIC design engineers working on signal integrity and power-grid analysis  of Valence HomePlug six million transistor chip, and responsible for Valence Family Radio System (FRS) baseband 2.5 million transistor chip in TSMC 0.25um CMOS, a full-digital  architecture with DSP-system power, speed and area optimization and integrated GPS data link, and in charge of its physical implementation including  layout delivery and manufacturability tests. November 2002-April 2003.

• Director, VLSI Design of Valence Integrated Gateway Architecture, Valence Semiconductor Inc., Dubai and Canada Offices: Developed architecture and implemented a dual ARM946-8888, 20-block memory, 20-millioin transistor ASIC for a flexible yet affordable voice-data gateway in TSMC 0.18um CMOS. Jan. 2001-September 2002.

• Consultant, Valence Semiconductor Inc.: Dubai and Canada Offices, Aug. 2000-Dec. 2000.

• Founding Director of VLSI Circuits and Systems Laboratory, the University of Tehran: Most-recent research included: Design and implementation of dedicated DSP hardware for digital subscriber lines (ADSL line-communication devices), and mobile-communication applications; design of custom­ized high-performance architectures for parallel DSP processors; development of several CMOS low-power logic  styles; implementation of analog artificial neural networks using submicron CMOS technolo­gies; design of new efficient architectures for FPGAs and FPGA applications in industrial environ­ments; networks of parallel processors and their applications. September 1996- June 2001.

• Executive Chair, the Twelfth IEEE International Conference on Mocroelectronics (ICM 2000), Tehran, Iran, Oct. 30- Nov. 2, 2000, Conference Proceedings available on IEEE Xplore site.

• Associate Chair of Graduate Studies: Department of Electrical and Computer Engineering, University of Tehran. September 1999-March 2000

• Director of Electronics Group:    Department of Electrical and Computer Engineering, University of Tehran, since Sep. 1996-March 2000.

• Assistant Professor: Department of Electrical and Computer Engineering, University of  Tehran. Taught graduate courses in advanced VLSI design, VLSI array processing, hardware implementation of neural networks and intelligent systems, BiCMOS circuit design, and RF Microelectronics. Courses taught include undergraduate Electronic Circuits, Digital Electronics, Computer-Aided Design of Digital Circuits, and VLSI System Design. September 1995-July 2004.

• Research Assistant: Optoelectronics Lab, University of Toronto. Sept. 1993-Aug. 1995.

• Research Assistant: Computer Integrated Manufacturing and VLSI Research Laboratories, University of Toronto. March 1991-August 1993.

• Teaching Assistant: Department of ECE, University of  Toronto, sessions 1991/1992, 1992/1993, 1993/1994, 1994/1995.

• Instructor: Department of ECE, University of Tehran. Feb. 1989-Dec. 1990.

• Project Manager: Electronics Research Centre, University of Tehran. Feb. 1987-Aug. 1989.

• Electrical Engineer: Electronics Research Centre, University of Tehran. Jan. 1986-Jan. 1987.

• Researcher: Electronics Research Centre, University of Tehran. Aug. 1984-Dec. 1986.

Special Skills:

• Architecture design of Network Processors and ASIC implementation of dedicated hardware for high-speed manipulation of networking protocols: (Achievement: Valence Gateway processor, emerged into IBG 20 million transistor product, 2001).

• Design with focus on extreme cost-performance efficiency of voice/data multi-protocol integrated home/office gateways (Achievement: Valence Integrated Broadband Gateway (IBG) product, 20 million transistors, 2002).

• Design and optimization of dedicated hardware for high-performance signal processing systems (Achievements: Baseband 2.5 million transistor chip of Valence FRS system (2003), UT-VLSI Lab Industrial Project: multi-protocol Flex/ERMES/POCSAG Pager chip (1999), and VLSI Lab ADSL baseband processors (2000)).

• Design and implementation of general-purpose DSP hardware for mobile communication applications (Achievements: VLSI Lab variants of DSP processors (1996-1999)).

• Integration and implementation of image processing systems (Privately-funded activity: FPGA implementation of PCI high-speed image acquisition and processing system for midical and dental imaging purposes (1999)).

• Development of wireless communication systems for sensor fusion, monitoring and control (VLSI Lab Industrial Project: Custom wireless communication system, FPGA-MCU ASIC preparation of baseband system and fabricated bipolar integrated front end (1997-1999)) .

• Design of dedicated hardware for one-way and two-way paging systems (Prepared working design on 8051 MCU/FPGA based platform for ASIC development environment (1998)).

• Application of DSP systems to industrial environments  (UT-VLSI Lab study based on developed ASIC designs (1997)).

• Industrial applications of Artificial Neural Networks (University of Toronto summer studies (1997-2000)).

• Simulation, design, hardware implementation, and after-fabrication programming and test of custom-designed neural-network hardware (University of Toronto(1994-1995)).

• Design and implementation of mixed analog-digital circuits (employing memories, buffers, multiplexers, and dedicated analog processing engines for intelligent systems (1993-1995).

• Certificate of Synopsys Inc. for VHDL synthesis and simulation training courses (1994).

• Full familiarity with Cadence integrated design environment including NCSim Verification, BuildGtes Extreme Synthesis and Power Optimization, SOC Encounter, Celtic crosstalk analysis, and Voltage Storm power grid analysis tools (used in making many digital and analog IC chips).

• Set up of the environment and teaching of VLSI design using MAGIC and LEDIT VLSI  design tools.

• Design, installation, programming, and maintenance of computer-controlled IC test systems.

• Programming experience with C language: writing system-level and behavioral simulators for pre-implementation studies. Some experience with C++.

• Extensive experience with MATLAB and its signal-processing and neural-network toolboxes.

• Familiarity with different PC-based and UNIX-based computational platforms.

• Design and programming of various analog and digital data acquisition systems.

• Working and programming of HP and Keithley semiconductor analysis instruments.

• Parallel programming and applications of parallel array processors.

• Integration and optimization of digital systems using integrated circuits technology.

Research Interests: Present and Future

• Intelligent Processor Convergence: I have had plenty of activities on design of general-purpose processors, DSP customized hardware engines, cores for intelligent systems, and network processors. In addition, I have designed and implemented several generations of mixed-mode neural network intelligent processing systems. Now, I wish to work on the idea of “Intelligent Processor Convergence,” in the context of the massive market for intelligent signal-processing and home/office networking products, a context that adopts the best of all worlds for highest cost/performnace to supply such pieces of hardware to improve the life of every human being.

• Network processor and broadband gateway architectures and their implementation: I have worked as director of an industrial team working on development of dedicated hardware and related software for highly integrated, high-speed, and  yet-affordable home gateway processors. I realize that there are many improvements and optimizations in architecture and implementation of gateway chips that would allow them to become an affordable integral part of every home in the world.

• Fully-optimized low-power DSP engines for communication systems: My previous experience includes development of custom engines for low-power FRS baseband chip; two-way and one-way multi-protocol paging systems; and a custom ADSL system.  These activities have led me to identify many improvements in DSP algorithms and their implementation which potentially open up new horizons for reducing area, power and system-integration costs while improving the performance.

• Manufacturability and Signal Integrity of ASIC chips: Having worked on the power grid analysis and signal integrity of the Valence six million transistor Home Plug ASIC chip, I have been in short of tools and methodologies to incorporate SI and power related timing considerations in the design cycle right from beginning of RTL synthesis and chip planning. Database convergence, virtual chip prototyping, concept of wire synthesis, realistic interconnect delay estimation, extra delay margins considered from the beginning, and rapid detail routing are all techniques that are partly investigated by Cadence and Synopsys, but none has been evolved into a mature design flow, and there are yet many flaws to fill.

• VLSI implementation of general DSP processors for communication applications:  Having directed a 15-member team working in collaboration with industry on design and VLSI implementation of a dedicated DSP processor for use in GSM mobile handsets, I am in a position to clearly recognize that the future mobile systems will constitute of a mixture of general processors and custom coprocessing hardware. This is a fact recognized by other researchers as well yielding to development of configurable-instruction processors and their required CAD tools. However, packetized-data mobile systems are in need of efficient packet processors as well. This is an area that I feel I am in a good position to contribute. I have worked on and have suggestions for many variants of such processors to be developed.

• Development of hardware-emulation systems and custom ASIC development boards:  Hardware and software have been developed at UT-VLSI lab to provide high-performance FPGA systems for rapid evaluation of complex digital systems with maximum capacity of 300,000 equivalent gates. Several  generations of this project have been constructed. The one with 100,000 equiva­lent-gate capacity has been used for DSP processor development emulation. Another embedded system with 8051 CPU, memory, and FPGA was developed and used in pager project. Nowadays, embedded system IP providers development systems (e.g. MIPS nad ARM) will make average users needless of custom developments. However, an active development team should come with the expertise and speed to assemble custom development environments. Such a need appears almost always at interfaces side even when using some existing development systems, as we have done with ARM Integrated System and our custom interfaces in Valence Semiconductor Inc.

• Hardware implementation of artificial neural networks (ANNs): Through theoretical analysis,  extensive simulations using our custom-designed neural network simulator written in C, HSPICE circuit simulations, development of a new device and its model, and several cycles of chip fabrication, we have designed a new class of efficiently-hardware-implementable ANNs that employ a single MOS transistor as their synaptic block. The whole idea has been verified by a 10,000-transistor final test chip including 15 neurons and 270 synapses connected in three layers. Development of denser and more integrated digitally-interfaced  analog-and-digital processing intelligent systems and neural networks are things that I see as future must-to-do activities.

• Mixed-mode implementation of ANNs in submicron CMOS technologies: Developed, fabricat­ed, and tested a 0.35um analog neural network with 3-D closed-boundary discriminat­ing surfaces for pattern  classification and recognition applications. This research has brought new ideas towards integration and application of mixed mode analog-digital massively parallel integrated systems with potential applications in intelligent systems and man-machine interface as outlined above.

Publications:

Books

1.  S. Mehdi Fakhraie and K.C. Smith, VLSI-Compatible Implementations for Artificial  Neural Networks. Boston: Kluwer Academic Publishers, 1997.

Papers (journal)

1. R. Rafati, S. Mehdi Fakhraie, and K. C. Smith, "A 16-bit barrel-shifter implemented in data-driven dynamic logic," in IEEE Trans. Circuits and Systems I: Regular papers, pp. 2194-2202, vol. 53, no. 10, Oct. 2006.

2. S. Rahimian Omam, S. M. Fakhraie, and O. Shoaei, “Minimizing the adder cost in multiple constant multipliers,” in IEICE Electronic Express, vol. 3, no. 14, pp. 340-346, July 2006.

3. A. Pedram, M. R. Jamali, T. Pedram, S. M. Fakhraie, and C. Lucas, “Local linear model tree (LOLIMOT) reconfigurable parallel hardware,” in Transactions on Engineering, Computing and Technology, Poland, vol. 13, pp. 96-101, May 2006.

4. E. Rohani and S. Mehdi Fakhraie, "Round-off error in block floating point structures," in IEE Electronics Letters, vol. 42, no. 3, Feb. 2006.

5. R. Rafati and S. Mehdi Fakhraie, "Data-driven dynamic logic," in Journal of the Faculty of Engineering of the University of Tehran, Fall 2005. (in Persian)

6. S. Shamshiri, S. M. Fakhraie, and C. Lucas, "A genetic-algorithm solution for designing optimal forwarding tables," in Nasir J. of Science and Engineering, vol. 1, no. 1, Summer 2005. (in Persian)

7. S. Shamshiri and S. M. Fakhraie, "Genetic algorithm memory minimization for designing reconfigurable address lookup engine," in Int. J. of  Computational Intelligence and Applications, Imperial College Press, vol. 5, no. 1, pp. 69-80, March 2005.

8. S. R. Abdollahi, S. M. Fakhraie,  and M. Kamarei, "A crystal-based low-voltage all-digital programmable ring oscillator," in Analog Integrated Circuits and Signal Processing, Springer Science (Formerly published by Kluwer Academic Publishers),  vol. 43, no. 2, pp. 147 – 157, May 2005.

9. S. M. Fakhraie, H. Farshbaf, and K.C. Smith, "Scalable closed-boundary analog neural networks," in IEEE Trans. Neural Networks, vol. 15, no. 2, pp. 492-504, March 2004.

10. Mehran Nadjarbashi, S. Mehdi Fakhraie, and Alireza Kaviani, “On routing architecture for hybrid FPGA,” in Int. J. of Science and Technology: Scientia Iranica, vol. 11, no. 3, pp. 159-164, Summer 2004.

11. M. H. Tehranipour, S. M. Fakhraie, M. R. Movahedin, and Z. Navabi, "A low-cost at-speed BIST architecture for embedded processor and SRAM cores," in Journal of Electronic Testing, Theory and Applications, Kluwer Academic Publishers, vol. 20, pp. 155-168, April 2004.

12. M. H. Tehranipour, S. M. Fakhraie, M. Nourani, Z. Navabi, and M. R. Movahedin, "Embedded test for processor and memory cores in system-on-chips," in Int. J. of Science and Technology: Scientia Iranica, vol. 10, no. 4, pp. 486-494, October 2003.

13. H. Zarei, O. Shoaei, and S. M. Fakhraie, “A 37-mW fully integrated GMSK modulator for DRRS standard in 0.6-um digital CMOS process,” in  IEEE Trans. Circuits and Systems II, vol. 49, no. 7, pp. 513-520, July 2002.

14. B. S. Biria, S. M. Fakhraie, and C. Lucas, “Improvement of neural networks generalization by adaptive regularization parameters,” in Amirkabir Journal of Science and Technology, vol. 11, no. 43, pp. 348-360, Spring 2000.

15. A. Shamaie, S. M. Fakhraie, and B. Benhabib, “A new technique for accurate estimation of partly-occluded-ellipse parameters,” in Int. J. of Science and Technology: Scientia Iranica, Electrical Engineering Issue, Fall 1999.

16. S. Mehdi Fakhraie, A. Konrad, and K.C. Smith, “Neuro-computation techniques in sampled-data electromagnetic-field problems,” in IEEE Trans. Magnetics, vol. 30, no 5, pp. 3637-3640, Sept.1994.

Papers (conference)

1. F. Montazeri, M. Salmani-Jelodar, S. N. Fakhraie, S. M. Fakhraie, "Evolutionary multiprocessor task scheduling," in Proc. PARELEC 2006, Poland, pp. 68-76, Sep. 2006.

2. A. Pedram, M. R. Jamali, S. M. Fakhraie, C. Lucas,"Reconfigurable parallel hardware for computing local linear neuro-fuzzy model," in Proc. PARELEC 2006, Poland, pp. 198-201, Sep. 2006.

3. A. Banaiyan, H.R. Mahdiani, and S. M. Fakhraie, "Software implementation issues of existing and new defuzzificztion methods," in Proc. 2006 IEEE World Congress Computational Intelligence, Vancouver, Canada, pp. 8476-8481, July 2006.

4. M. Salmani Jelodar, Najmeh Fakhraie, Faeze Montazeri, S. Mehdi Fakhraie, M. Nili Ahmadabadi, "A representation for genetic-algorithm-based multiprocessor task scheduling," Proc. 2006 IEEE World Congress Computational Intelligence, Vancouver, Canada, pp. 1044-1051, July 2006.

5. M. Salmani Jelodar, Mehdi Kamal, S. Mehdi Fakhraie, M. Nili Ahmadabadi, "SOPC-based parallel  genetic algorithm," in Proc. 2006 IEEE World Congress Computational Intelligence, Vancouver, Canada, pp. 9705-9711, July 2006.

6. A. Banaiyan, H. R. Mahdiani, and S. Mehdi Fakhraie, "PiFie: A platform-independent fuzzy instruction set extension," in Proc. NAFIPS06, Montreal, Canada, June 2006. 

7. A. Banaiyan, M. Salmani Jelodar, and S. Mehdi Fakhraie, "ISA extension to general purpose processors for fuzzy and genetic algorithm applications," in Proc. NAFIPS06, Montreal, Canada, June 2006.

8. H. Esmaeilzadeh, P. Saeedi, B. N. Araabi, C. Lucas, and S. M. Fakhraie, “Neural network stream processing core (NnSP) for embedded systems,”  Proc. IEEE Int. Symposium Circuits and Systems (ISCAS06), pp. 2773-2776, Island of KOS, Greece, May 2006.

9. H. Esmaeilzadeh, A. Moghimi, E. Ebrahimi, C. Lucas, Z. Navabi, and S. M. Fakhraie, “DCim++: A C++ library for object oriented hardware design and distributed simulation,” Proc. IEEE Int. Symposium Circuits and Systems (ISCAS06), pp. 1283-1286, Island of KOS, Greece, May 2006.

10. F. Kashfi, and S. M. Fakhraie, “Implementation of a high-speed low-power 32-bit adder in 70nm technology,” Proc. IEEE Int. Symposium Circuits and Systems (ISCAS06), pp. 9-12, Island of KOS, Greece, May 2006.

11. H. R. Mahdiani, A. Banaiyan, and S. M. Fakhraie, “Hardware implementation and    Symposium Circuits and Systems (ISCAS06), pp. 4619-4622, Island of KOS, Greece, May 2006.

12. M. Salmani Jelodar, S. M. Fakhraie, and M. Nili Ahmadabadi, "Two-stage morphological filter design using genetic algorithms," Proc. IEEE Int. Conf.  Engineering of Intelligent Systems (ICEIS06), pp. 129-133, Islamabad, Pakistan, May 2006.

13. H. Holisaz, S. Shamshiri, F. Baharvand, and S. Mehdi Fakhraie, "Hardware Accelerator IP core for wireless 802.16 MAC," in Proc. Third Wireless and Optical Communication Networks (WOCN), pp. 1-5, India, April 2006.

14. H. Hollisaz, N. Moezzi Madani, and S. Mehdi Fakhraie, "A quantitative approach to digital filter implementation," Proc. IEEE International Conference on Microelectronics 2005, pp. 160-164, Pakistan, Dec. 2005.

15. N. Moezzi-Madani, E. Rohani, and S. Mehdi Fakhraie, "Hardware considerations for digital audio broadcasting system," Proc. IEEE International Conference on Microelectronics 2005, pp. 209-212, Pakistan, Dec. 2005.

16. S. M. Mortazavi Zanjani, S. M. Fakhraie, and O. Shoaei, "A comparative study and design of decimation filter for high-precision audio data converters," Proc. IEEE International Conference on Microelectronics 2005, pp. 139-143, Pakistan, Dec. 2005.

17. M. Nazm-Bojnordi, N. Sedaghati-Mokhtari, and S. Mehdi Fakhraie, "A self-testing fully pipelined implementation for the advanced encryption standard," Proc. IEEE International Conference on Microelectronics 2005, pp. 260-263, Pakistan, Dec. 2005.

18. N. Moezzi Madani, J. Hadi, and S. Mehdi Fakhraie, "Design and implementation of a fully digital 4FSK demodulator," Proc. European Conference on Circuit Theory and Design, pp. 277-280, Ireland, Dec. 2005.

19. A. Banaiyan, H.R. Mahdiani, and S.M. Fakhraie, "Cost-performance co-analysis in VLSI implementation of existing and new defuzzification methods," Proc. International Conference on Computational Intelligence for Modeling Control and Automation – CIMCA, Austria, Nov. 2005.

20. E. Rohani and S. M. Fakhraie, "Reducing round-off error in an ADSL modem with block-floating-point structure," in Proc. International Symposium on Telecommunications (IST2005), Shiraz, Iran, Sep. 2005.

21. M. Alisafaee, S. Ataee, S. M. Fakhraie, "Bandwidth-enhanced waste-free control technique for multi-queue network buffers," in Proc. International Symposium on Telecommunications (IST2005), Shiraz, Iran, Sep. 2005.

22. G. R. Chaji, S. M. Fakhraie, "A low-power high-performance digital circuit for deep submicron technologies," Proc. IEEE NEWCAS05, Quebec, Canada, June 19-22, 2005.

23. M. Alisafaee, and S. M. Fakhraie, Mohammad Tehranipoor "Architecture of an embedded queue management engine for high-speed network devices," Proc. 2005 IEEE Int’l Midwest Symposium on Circuits and Systems,  Cincinnati, USA, Aug. 2005.

24. Hadi Esmaeilzadeh, Farhang Farzan, Neda Shahidi, Sied Mehdi Fakhraie, Caro Lucas, and Mohammad Tehranipoor, " NnSP: Embedded neural networks stream processor," Proc. 2005 IEEE Int’l Midwest Symposium on Circuits and Systems,  Cincinnati, USA, Aug. 2005.

25. Saeed Shamshiri, S. Mehdi Fakhraie, and Zainalabedin Navabi, "Designing optimal forwarding tables with genetic algorithm," Proc. ACM SIGCOMM Workshop 2005, Beijing, China, April 2005.

26. Mehdi Salmani Jelodar, Sied Mehdi Fakhraie, and Majid Nili Ahmadabadi, "A new approach for training of artificial neural networks using population based incremental learning (PIBL), Proc. of the Int. Conf. Computational Intelligence (ICCI 2004), Istanbul, Turkey, pp. 165-168, Dec. 2004.

27. Hadi Esmaelzadeh, Hamed Farshbaf, Caro Lucas, and Sied Mehdi Fakhraie, "Digital implementation for conic section function networks," Proc. IEEE Int. Conf. Microelectronics 2004 (ICM2004), Tunis, Tunisia, pp. 564-567, Dec. 2004.  

28. S. Shamshiri, and Sied Mehdi Fakhraie, "Parallel alias reduction for MP3 decoding," Proc. IEEE Int. Conf. Microelectronics 2004 (ICM2004), Tunis, Tunisia, pp. 438-441, Dec. 2004.  

29. M. Ghannad Rezaie, F. Farbiz, and Sied Mehdi Fakhraie, "An analytical approach to hardware-friendly adaptive learning rate neural networks," Proc. IEEE Int. Conf. Microelectronics 2004 (ICM2004), Tunis, Tunisia, pp. 320-323, Dec. 2004.

30. S. Shamshiri, S. Mehdi Fakhraie, and C. Lucas, "A genetic algorithm solution for designing optimal forwardign tables," Proc. Sixth Conf. Intelligent Systems (CIS 2004), Kerman, Iran, Nov. 2004.

31. S. R. Abdollahi, S. M. Fakhraie, M. Kamaeri, and S. E. Abdollahi, "A 68MHz multi-channel all-digital programmable oscillator," Proceedings 2003 10th IEEE International Conference on  Electronics, Circuits and Systems, 2003 (ICECS 2003),vol. 2 , pp. 475-478, 14-17 Dec. 2003.

32. S. R. Abdollahi, M. Kamaeri, and S. M. Fakhraie, "Semi-coherent GFSK receiver for DECT standard," Proceedings 2003 10th IEEE International Conference on  Electronics, Circuits and Systems, 2003 (ICECS 2003),vol. 3 , pp. 1244-1247, 14-17 Dec. 2003.  

33. Seyed Reza Abdollahi, Seyed Mehdi Fakhraei, Bertan Bakkaloglu, and Mahmoud Kamarei,  "A crystal-based digital ring oscillator," Proceedings 2003 IEEE International Conference on Field-Programmable Technology (FPT), Tokyo, Japan, pp. 319-323, Dec. 15-17, 2003.

34. Mohammad Tehranipour, Mehrdad Nourani, Mehdi Fakhraie, and Ali Afzali-Kusha, “Systematic test program generation for SoC testing using embedded processors,” ISCAS 2003, Bangkok, Thailand, vol. 5, pp. 541-544, May 2003.

35. G. R. Chaji, R. M. Pourrad, S. M. Fakhraie, and M. H. Tehranipour, “EUTDSP: A design study of a new VLIW-based DSP architecture,” ISCAS 2003, Bangkok, Thailand, vol. 4, pp. 137-140, May 2003.

36. S. M. Fakhraie, M. H. Tehranipour, M. R. Movahedin, and M. Nourani,  "Fast prototyping of a DSP core," 45th Midwest Symposium on Circuits and Systems, vol. 2, Page(s): 215 -218, 2002.

37. M. H. Tehranipour, M. Nourani, S. M. Fakhraie, and C. A. Papachristou, "Test optimization of bus-structured SoCs using embedded processor," 45th Midwest Symposium on Circuits and Systems, vol. 1, Page(s): 168-171, 2002.

38. R. Rafati, A. Z. Charaki, G. R. Chaji, S. M. Fakhraie, and K. C. Smith, “Comparison of a 17b multiplier in dual-rail Domino and dual-rail D3L logic styles,” ISCAS 2002, Scottsdale, Arizona, vol. 3, pp. 257-260, May 26-29 2002.

39. G. R. Chaji, S. M. Fakhraie, and K. C. Smith, “Pseudo dynamic logic (SDL):  A high-speed and low-power logic family,” ISCAS 2002, Scottsdale, Arizona, vol. 3, pp. 245-248, May 26-29 2002.

40. S. R. Abdollahi, S. M. Fakhraie, and Sayfe Kiaei, “An all-digital programmable digitally-controlled-oscillator (DCO) for digital wireless applications,” ISCAS 2002, Scottsdale, Arizona, vol. 4, pp. 101-104, May 26-29 2002.

41. G. R. Chaji, S. M. Fakhraie, and K. C. Smith, “High-speed low-power adder design with a new logic style: Pseudo Dynamic Logic (SDL),” Proc. IEEE Int. Conf. Microelectronics 2001 (ICM2001), (Rabat, Morocco), Oct.29-31 2001.

42. H. R. Mahdiany, A. Hormati, and S. M. Fakhraie,  “A hardware accelerator for DSP system design: University of Tehran DSP hardware emulator (UTDHE),” Proc. IEEE Int. Conf. Microelectronics 2001 (ICM2001), (Rabat, Morocco), Oct.29-31 2001.

43. M. Tehranipour, Z. Navabi, and S. M. Fakhraie, “A low-cost BIST architecture for microprocessor/DSP cores,” Proc. Third Electronics Circuits and Systems Conf. (ECS’01), (Bratislava, Slovakia), Sep. 5-7 2001.

44. H. Zarei, O. Shoaei, and M. Fakhraie, “A low-power fully integrated Gaussian-MSK modulator based on the sigma-delta fractional-N frequency synthesis,” Proc. ISCAS 2001 (Sydney, Australia), vol. 4, pp. 100-103, May 2001.

45. M. Tehranipour, Z. Navabi, and S. M. Fakhraie, “An efficient BIST method for testing of embedded SRAMs,” Proc. ISCAS 2001, (Sydney, Australia), vol. 5, pp. 73-76, 6-9  May 2001.

46. H. Zarei, O. Shoaei, S. M. Fakhraie, and M. M. Zakeri, “A 1.4 GHz/ 2.7 V programmable frequency divider for DRRS standard in 0.6 /spl mu/m CMOS process,” Proc. 7th IEEE International Conference on Electronics, Circuits and Systems, 2000, (ICECS 2000), (Jounieh, Lebanon), vol. 2, pp. 887 –890, Dec. 2000.

47. S. R. Abdollahi, S. M. Fakhrai, and M. M. Zakeri, “Performance of phase locked loop GFSK demodulator in a multipath channel,” Proc. 3rd Int. Symp. Wireless Personal Multimedia Communications (WPMC’00), (Bangkok, Thailand), pp. 825-829, Nov. 12-15, 2000.

48. S. A. Khodaian, S. H. Jamali, R. Hoshyar, M. Fakhrai, and A. S. Bahai, “Threshold LogMAP SISO block for FPGA implementation of turbo decoder,” Proc. 3rd Int. Symp. Wireless Personal Multimedia Communications (WPMC’00), (Bangkok, Thailand), pp. 538-542, Nov. 12-15, 2000.

49. R. Rafati, A. Z. Charaki, S. M. Fakhraie, and K. C. Smith, “Data-driven dynamic logic versus NP-CMOS logic, a comparison,” Proc. Twelfth IEEE Int. Conf. Microelectronics (ICM’2000), (Tehran, Iran), pp. 57-60, Oct. 31-Nov. 2, 2000.

50. Mehran Nadjarbashi, S. Mehdi Fakhraie, and Alireza Kaviani, “On routing structure for the hybrid field programmable architecture,” Proc. Twelfth IEEE Int. Conf. Microelectronics (ICM’2000), (Tehran, Iran), pp. 259-264, Oct. 31-Nov. 2, 2000.

51. Hossein Zarei, Omid Shoaei, S. M. Fakhraie, and M. M. Zakeri, “A low-power multi-modulus divider in 0.6um digital CMOS technology,” Proc. Twelfth IEEE Int. Conf. Microelectronics (ICM’2000), (Tehran, Iran), pp. 359-362, Oct. 31-Nov. 2, 2000.

52. M. Haji-rostam, M. Maddah-Ali, A. Haft-Baradaran, M. T. Kilani, S. M. Fakhraie, M. Sharifkhani, and O. Shoaei, “Kalman-filtering timing recovery scheme for orthogonal frequency domain multiplexing (OFDM) systems,” Proc. ICASSP’2000, (Istanbul, Turkey), pp. V-2681-2684, June 5-9 2000.

53. R. Rafati, S. M. Fakhraie, and K. C. Smith, “Low-power data-driven dynamic logic (D3L),” Proc. ISCAS’2000, (Geneva, Switzerland), pp. I-752-755, 28-31 May 2000.

54. F. Bahmani, S. M. Fakhraie, and A. Khakifirooz, “A rail-to-rail one-Volt constant-Gm CMOS opamp,” Proc. ISCAS’2000, (Geneva, Switzerland), pp. II-669-672, 28-31 May 2000.

55. A. Kheirkhahi, S. M. Fakhraie, and M. Kamarei, “Algorithmic design of a 900 MHz CMOS RF power amplifier introducing SPICE-Smith chart method,” Proc. European Solid State Circuits Conference 1999 (ESSCIRC’99), (Germany), 17-20 Sept. 1999.

56. O. Nasibi, M. Nourani, S. M. Fakhraie, A. Zakeri, and A. Ghalambor-Dezfoli, “Multi-access integrated memory management for deeply-pipelined processors,” Proc. Eleventh IEEE Int. Conf. Microelectronics (ICM’99), (Kuwait), pp. 285-289, 22-24 Nov. 1999.

57. M. Samady, M. Movahedin, S. M. Fakhraie, Z. Navabi, and A. Ghalambor-Dezfoli, “Implementation of serial port interconnections for integrated circuits,” Proc. Eleventh IEEE Int. Conf. Microelectronics (ICM’99), (Kuwait), pp. 291-294, 22-24 Nov. 1999.

58. A. Kheirkhahi, S. M. Fakhraie, and M. Kamarei, “A low-voltage high efficiency digitally programmable DC/DC converter,” Proc. Eleventh IEEE Int. Conf. Microelectronics (ICM’99), (Kuwait), pp. 281-284, 22-24 Nov. 1999.

59. F. Bahmany, and S. M. Fakhraie, “A rail-to-rail 1-Volt CMOS opamp,” Proc. Eleventh IEEE Int. Conf. Microelectronics (ICM’99), (Kuwait), pp. 217-219, 22-24 Nov. 1999.

60. A. Sodagar, S. M. Fakhraie, and K. C. Smith, “A low-voltage Current-Controlled Oscillator with low supply dependency,” Proc. Tenth IEEE Int. Conf. Microelectronics (ICM’98), (Monastir, Tunisia), pp. 282-285, Dec. 14-16, 1998.

61. A. H. Abutalebi, and S. M. Fakhraie, “A submicron analog neural network with an adjustable-level output unit,” Proc. Tenth IEEE Int. Conf. Microelectronics (ICM’98), (Monastir, Tunisia), pp. 294-297, Dec. 14-16, 1998.

62. F. Baharvand, and S. M. Fakhraie, “A reduced lookup table for SRAM-based FPGA logic blocks,” Proc. Ninth IEEE Int. Conf. Microelectronics (ICM’97), (Bandung, Indonesia), pp. 138-141, Oct. 8-10, 1997.

63. A. H. Abutalebi, and S. M. Fakhraie, “Submicron analog multipliers: Overview, comparison, and modelling,” Proc. Ninth IEEE Int. Conf. Microelectronics (ICM’97), (Bandung, Indonesia), pp. 85-88, Oct. 8-10, 1997.

64. S. Mehdi Fakhraie, J. M. Xu, and K. C. Smith, “Design and implementation of SynapseMOS (SyMOS) Artificial Neural Networks,” Proc. Eighth Int. Conf. Microelectronics (ICM’96), (Cairo, Egypt), pp. 71-74, Dec. 14-16, 1996.

65. S. Mehdi Fakhraie, J. M. Xu, and K. C. Smith, “Application of analog quadratic neural networks (AQNNs) to function approximation problems,” Proc. Int. Conf. Intelligent and Cognitive Systems, (Tehran, Iran), pp. 43-48, Sep. 1996.

66. S. Mehdi Fakhraie, J. M. Xu, and K. C. Smith, “Design of CMOS Quadratic Neural Networks,” Proc. IEEE Pacific Rim Conf. on Communications, Computers, and Signal Processing, (Victoria, BC, Canada) May 17-19, 1995.

67. S. Mehdi Fakhraie, K. C. Smith, and J. M. Xu, “Comparison of three different architectures for MOS-Compatible quadratic synapses,” Proc. IEEE Int. Symp. Speech, Image Processing, and Neural Networks, (Hong Kong), pp. 483-6, April 13-16, 1994.

68. S. Mehdi Fakhraie, and K. C. Smith, “Synapse-MOS (SyMOS) Transistors: Intelligent MOS transistors with learning thresholds,” Proc. Canadian Conf. VLSI’93 (Banff, Alberta, Canada), pp. 7.28-33, Nov. 14-16, 1993.

69. S. Mehdi Fakhraie, A. Konrad, and K. C. Smith, “Application of neuro-computation techniques to sampled-data electromagnetic-field problems,” Records of the Ninth COMPUMAG Conf., (Miami, Florida), pp. 72-73, Nov. 1993.

70. S. Mehdi Fakhraie, and K. C. Smith, “Generalized artificial neural networks,” Proc. Canadian Conf. Elec. and Comp. Eng. (Vancouver, BC, Canada), pp. 469-472, Sept. 14-17, 1993.

Reviewed Conference Papers (Published in the Proceedings of Local Conferences):

1. P. Saeedy and S. M. Fakhraie, "Coprocessor for genetic algorithms," in Proc. 14^th Iranian Conf. Electrical Engineering (ICEE2006), Tehran, Iran, April 2006.

2. N. Sedaghati-Mokhtari, S. Rahmanian, and S. M. Fakhraie, "Hardware implementation analysis for digital filters," in Proc. 14^th Iranian Conf. Electrical Engineering (ICEE2006), Tehran, Iran, April 2006.

3. M. Salehi, M. Najibi, H. Pedram, A. Afzali-Kousha, and S. M. Fakhraie, "Implementation of dynamic control system for voltage and frequency for power reduction of processors," in Proc. 14^th Iranian Conf. Electrical Engineering (ICEE2006), Tehran, Iran, April 2006 (in Persian).

4. M. Salmani Jelodar, H. Kamal, S. M. Fakhraie, and M. Nili Ahmadabadi, "SOPC-based parallel genetic algorithm," in Proc. 14^th Iranian Conf. Electrical Engineering (ICEE2006), Tehran, Iran, April 2006.

5. Sedigheh Hashemi and S. M. Fakhraie, "A novel technique for design and optimization of FIR digital filters using genetic algorithms," in Proc. 14^th Iranian Conf. Electrical Engineering (ICEE2006), Tehran, Iran, April 2006.

6. H. Parande Afshar, S. Mehdi Fakhraie, "Parallel merged multiplier-accumulator coprocessor optimized for audio filters," in Proc. Conf. 11^th International CSI Computer Conference (CSICC' 2006), Tehran, Iran, Jan. 2006.

7. M. Salmani Jelodar, S. Mehdi Fakhraie, M. Nili Ahmadabadi, "Improving morphological filters by intelligent algorithms," in Proc. Conf. Computational Intelligence, Tehran, Iran, 2005.

8. H. Esmailzadeh, A. Pedram, A. Alaghi, B. N. Araabi, C. Lucas, and S. M. Fakhraie, "Neural network parallel data flow processor architecture," Proc. 13^th Iranian Conf. Electrical Engineering (ICEE2005), Zanjan, Iran, May 2005.

9. M. B. Vahidfar, S. M. Fakhraie, and M. Fardis, "Delta sigma enhanced, low SFDR, area efficient digital FM modulator," Proc. 13^th Iranian Conf. Electrical Engineering (ICEE2005), Zanjan, Iran, vol. 1, pp. 427-430, May 2005.

10. M. AliSafaee, and S. M. Fakhraie, "Design and alalysis of a double bandwidth memory for network routers and switches," Proc. 13^th Iranian Conf. Electrical Engineering (ICEE2005), Zanjan, Iran, May 2005 (in Persian).

11. M. Alisafaee, Z. Navabi, and S. M. Fakhraie, "Doubling memory bandwidth for single-queue network buffers using uniform distribution methods," Proc. 10^th Annual CSI Conf. (CSICC'2005), Tehran, Iran,  pp. 172-179, Feb. 2005.

12. H. Kalantari, H. pedram, and S. M. Fakhraie, "A methof for  high-level energy estimation in template-based QDI asynchronous circuits," Proc. 10^th Annual CSI Conf. (CSICC'2005), Tehran, Iran,  pp. 180-187, Feb. 2005.

13. S. shamshiri, and S. M. Fakhraie, "Enhanced full expansion compression method for fast IP address lookup with minimum memory consumption,"  Proc. 10^th Annual CSI Conf. (CSICC'2005), Tehran, Iran,  pp. 212-221, Feb. 2005.

14. M. Haji-Rostam, M. A. Maddah-Ali, A. Haft-Baradaran, M. T. Kilani, S. M. Fakhraie, M. Sharifkhani, O. Shoaei, “A robust timing recovery scheme based on Kalman-filtering for OFDM systems,” Proc. Eighth Iranian Conf. Electrical Engineering, (Isfahan, Iran), pp. vol. 4, pp. 87-92, May 17-19, 2000.

15. M. Haji-Rostam, M. Sharifkhani, A. Haft-Baradaran, M. T. Kilani, O. Shoaei, S. M. Fakhraie, A. Adibi, “System design of an ADSL modem based on ANSI T1.413,” Proc. Eighth Iranian Conf. Electrical Engineering, (Isfahan, Iran), vol. 4, pp. 173-180, May 17-19, 2000.

16. H. Zarei, M. M. Zakeri, O. Shoaei, S. M. Fakhraie, “Design of a multi-modulus fractional-N low-power high-speed frequency divider,” Proc. Eighth Iranian Conf. Electrical Engineering, (Isfahan, Iran), May 17-19, 2000.

17. R. Rafati, S. M. Fakhraie, “Data-driven dynamic logic (D3L),” Proc. Seventh Iranian Conf. Electrical Engineering, (Tehran, Iran), pp. Ele. 61-68, 17-19 May, 1999.

18. A. Kheirkhahi, S. M. Fakhraie, M. Kamarei, “Design of CMOS-RF power amplifiers using SPICE-Smith chart method,” Proc. Seventh Iranian Conf. Electrical Engineering, (Tehran, Iran), pp. Ele.29-36, 17-19 May, 1999.

19. M. Samady, S. M. Fakhraie, Z. Navabi, A. Ghalambor-Dezfoli, “Modelling and hardware implementation of a FIR filter with programmable architecture,” Proc. Seventh Iranian Conf. Electrical Engineering, (Tehran, Iran), 17-19 May, 1999.

20. B. Sajadi-Birea, S. M. Fakhraie, “Application of generalization-enhancement techniques to hand-written character recognition,” Proc. Fourth Annual International Conf. Computer Society of Iran, (Tehran, Iran), Dec. 23-25, 1998.

21. A. H. Abutalebi, S. M. Fakhraie, “Universal characterization of a basic differential stage and a Gilbert multiplier by a general functional MOS model,” Proc. Sixth Iranian Conf. Electrical Engineering, (Tehran, Iran), pp. III67-72, 12-14 May, 1998.

22. A. Sodagar, S. M. Fakhraie, “Design of a digital CCO with low supply dependency,” Proc. Sixth Iranian Conf. Electrical Engineering, (Tehran, Iran), pp. III73-77, 12-14 May, 1998.

23. S. Safari, and S. M. Fakhraie, “Design of a hardware accelerator for Viterbi algorithm,” Proc. Sixth Iranian Conf. Electrical Engineering, (Tehran, Iran), pp. III99-104, 12-14 May, 1998.

24. B. Sajadi-Birea, S. M. Fakhraie, “A generalization enhancement method for artificial neural networks in function approximation applications,” Proc. Sixth Iranian Conf. Electrical Engineering, (Tehran, Iran), 12-14 May, 1998.

25. F. Baharvand, and S. M. Fakhraie, “Design of an optimized architecture for the logic blocks of FPGA ICs,” Proc. Third Annual International Conf. Computer Society of Iran, (Tehran, Iran), pp. 206-214, Dec. 23-25, 1997.

26. B. Alizadeh, S. M. Fakhraie, and Z. Navabi, “Rapid design of complex VLSI systems by using a multi-level simulation environment in VHDL,” Proc. Third Annual International Conf. Computer Society of Iran, (Tehran, Iran), pp. 221-228, Dec. 23-25, 1997.

27. Atid Shamaie, S. M. Fakhraie, and B. Benhabib, “Accurate estimation of partly-occluded ellipse Parameters,” Proc. Fifth Iranian Conf. on Electrical Engineering, (Tehran, Iran), pp. 5-24-33, May 7-9, 1997.

28. F. Baharvand, and S. M. Fakhraie, “On designing reduced lookup tables for logic blocks of SRAM-based FPGAs,” Proc. Fifth Iranian Conf. on Electrical Engineering, (Tehran, Iran), pp. 1-178-186, May 7-9, 1997.

29. S. Mehdi Fakhraie, J.M. Xu, and K.C. Smith, “Design of a new class of CMOS-compatible artificial neural networks,” Proc. Fourth Iranian Conf. on Electrical Engineering, (Tehran, Iran), pp. 489-97, May 1996.

30. A. Khalili, S. Mehdi Fakhraie, “A compact serial/parallel systolic array multiplier,” Proc. Second CSI Computer Conference (CSICC’96), (Tehran, Iran), pp. 132-7, Dec. 24-26, 1996.

Presentations:

1. H. Mahdiani, A. Banaiyan, and S. M. Fakhraie, " Hardware implementation and comparison of new defuzzification techniques in fuzzy processors," IEEE ISCAS'06, Greece, May 2006.
2. H. Esmaeilzadeh, A. Moghimi, E. Ebrahimi, C. Lucas, Z. Navabi, and S. M. Fakhraie, "DCim++: a C++ library for object oriented hardware design and distributed simulation," IEEE ISCAS'06, Greece, May 2006.
3. H. Esmaeilzadeh, P. Saeedi, N. Arabi, C. Lucas, and S. M. Fakhraie, " Neural network stream processing core (NnSP) for embedded systems," IEEE ISCAS'06, Greece, May 2006.