Pooya Saeedi

         

         M.Sc. Candidate, Computer Engineering (Computer Architecture)

         School of Electrical and Computer Engineering

         University of Tehran, 14395-1465, Iran

                  Email: p.saeedi@ece.ut.ac.ir

                 

Short Biography:              

Pooya Saeedi was born in 1982 in Tehran, Iran. He received the B.Sc. degree in Computer Hardware Engineering in 2005 as a top student from University of Tehran, Tehran, Iran. Since 2005, he is an M.Sc. student of Computer Architecture at University of Tehran, Tehran, Iran. He is a research assistant in SILAB, School of ECE, University of Tehran. He works on designing and implementing hardware engines for bio-inspired algorithms under the supervision of Dr. Sied Mehdi Fakhraie and Dr. Siamak Mohammadi. His research interests include reconfigurable computing, bio-inspired computing, on-chip multiprocessing, parallel architectures, computer aided design, HW/SW codesign, network-on-chip and application specific hardware cores.
 

Education :                

             2005 – Now:   M.Sc., Computer Engineering, University of Tehran (UT), Tehran, Iran.

                          Thesis Title:         High-Performance NoC Interconnect Systems in Multi-Processor Environments

                        Advisor:              Dr. S. Mehdi Fakhraie, Associate Prof., email: fakhraie@ut.ac.ir

                        Co-Advisor:         Dr. S. Mohammadi, Assistant Prof., email: smohamadi@ece.ut.ac.ir

             2001 – 2005:   B.Sc., Computer Hardware Engineering, University of Tehran, Tehran, Iran.

                        Project Title:        Surveying Genetic Algorithm Executions from Hardware View and Designing a CoProcessor for Genetic Algorithms

                       Advisor:               Dr. S. M. Fakhraie, Associate Professor, email: fakhraie@ut.ac.ir

             1998 – 2001:   High School, Mathematics and Physics, Kamal High School, Tehran, Iran.

            

Research Interests

  • Reconfigurable Computing

  • Bio-Inspired and Intelligent Computing

  • System-On-a-Chip (SOC) Design and On-Chip Multiprocessing (CMP)

  • Parallel Hardware Architectures

  • Computer Aided Design (CAD)

  • FPGA/ASIC Design

  • HW/SW Codesign and Embedded Systems Design

  • Application Specific Hardware Cores

    •

    Network-on-Chips

    Research and Work Experiences:

    Sep. 2005 – Now: Research Assistant, Silicon Intelligence Lab., School of ECE, University of Tehran, Tehran, Iran.

    Fall 2006: Teacher Assistant, Logical Circuits, School of ECE, University of Tehran, Tehran, Iran.

            Publications:

       Journal Paper

    1. P. Saeedi, H. Katebi, S. Mohammadi, and S. M. Fakhraie, “High Performance System-on-Chip Architecture for Scalable Intelligent Computing,” Submitted toElsevier Artificial Intelligence, 2008.

       Conference Papers

    1. P. Saeedi, H. Esmaeilzadeh, S. Mohammadi, and S. M. Fakhraie, “Scalable Neural Network Stream Processor,” in Proc. of the East-West Design and Test Symposium. (EWDTS’07), Yerevan, Armenia, Sep. 2007, pp. 608-612.
       

    2. H. Esmailzadeh, M. R. Jamali, P. Saeedi, A. Moghimi, C. Lucas, and S. M. Fakhraie, “NnEP, Design Pattern for Neural-Network-Based Embedded Systems,” in Proc. IEEE Intl. Conf. on Mixed Design of Integrated Circuits and Systems (MIXDES’07), Jun. 2007, pp. 673-678.
       

    3. P. Saeedi, A. Farmahini-Farahani, M. Hamzeh, and A. Afzali-Kusha, “Network-on-Chip Thermal Balanced Mapping,” in Proc. IEEE Intl. Design and Test Workshop (IDT’06), Dubai, UAE, Nov. 2006.
       

    4. H. Esmailzadeh, P. Saeedi, B. N. Araabi, C. Lucas, and S. M. Fakhraie, “Neural Network Stream Processing Core (NnSP) for Embedded Systems,” in Proc. IEEE Intl. Symp. on Circuits and Systems (ISCAS’06), Island of Kos, Greece, May. 2006.
       

    5. M. H. Neishabouri, M. Hamzeh, A. Farmahini-Farahani, P. Saeedi, M. Daneshtalab, and N. Yazdani, “Voltage Scheduling Technique during System Level Design Using UML-RT Model,” in Proc. IEEE Design and Test Workshop, Dubai, UAE, Nov. 2006.
       

    6. H. Esmailzadeh, S. Shamshiri, P. Saeedi, and Z. Navabi, “ISC: Reconfigurable Scan-cell Architecture for Low Power Testing," in Proc.
      IEEE Asian Test Symposium (ATS’05)      , Kolkata, India, Dec. 2005, p236-241.
       

    7. H. Esmailzadeh, S. Shamshiri, P. Saeedi, E. Ebrahimi, A. Pedram, and Z. nabavi, “Interleaved Scan-Cell Architecture for Low Power Test,” in Proc. IEEE Workshop on Register Transfer Level Test (WRTLT’04), Osaka, Japan, Nov. 2004, pp. 123-128.
       

    * Papers available upon request

    Last update: Nov. 16, 2007.