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Baseband and DSP engines are at the heart of any modern communication system. Translating complicated descriptions of a describing protocol into efficient and optimized computational engines with optimized power-delay-area-yield-test features is a valuable expertise that we have built in this lab. As the following list prescribes, in most of the major communication paradigms, including LAN, WAN, PAN, wired and wireless varieties, we have developed system level simulators, prepared optimized bit-true modeling means, and based upon which have prepared ASIC and FPGA implementations. Alternative design tradeoffs at system, bit-width and algorithm determination, and implementation levels are explored and investigated. The following list shows a sample of the performed research. Wireless LAN 802.11 |