RASOUL YOUSEFI
School of Electrical and Computer Engineering
University of Tehran, Tehran, Iran.
Contact:
First Name: Rasoul
Family Name: Yousefi
Birth/Place: 22 September 1983 (1362/6/31)/ Iran
Nationality: Iranian
Email: r.yousefi@ece.ut.ac.ir
Fall 2006 – present: M.Sc., Electrical Engineering, University of Tehran (UT), Tehran, Iran.
GPA: 18.38 out of 20(so far) (Among 3 top M.Sc students of the Electrical/Electronic engineering of the University of Tehran)
Thesis Title: Online test of VLSI digital signal processing systems[ Thesis Abstract]
Advisor: Dr. S. Mehdi Fakhraie, Associate Prof., email: fakhraie@ut.ac.ir
Fall 2001 – 2006: B.Sc., Electrical Engineering, Shiraz University, Shiraz, Iran.
GPA: 14.81 out of 20
Fall 1997 – 2001: Diploma, Mathematics and Physics, Tohid-1 Special Talented High School, Shiraz, Iran.
GPA: 19 out of 20
Journal:
Morteza Damavandpeyma, Rasoul Yousefi and Behjat Forouzandeh,"Delay testing of PD-SOI circuits", IEICE Electron. Express, Vol. 5, No. 12, pp.437-441, 2008.
Conferences:
R. Yousefi, S. M. Fakhraie, “Frequency domain concurrent error detection in DSP systems,” Accepted in Innovations ’08, 2008.
R. Yousefi, S. M. Fakhraie, “Online and offline test unification in digital filters,” Accepted in Innovations ’08, 2008.
R. Yousefi, A. Ahmadi, S. M. Fakhraie, “Design flow for hardware implementation of digital filters,” in the forth international symposium on telecommunications, p.
586-591, Aug. 2008.
R. Yousefi, S. M. Fakhraie, “Frequency domain testing: a new approach in online test of VLSI digital Signal Processing Systems,” Accepted in ICCET 2009.
A. Jalili, R. Yousefi, S. M. Fakhraie, “Effect of different mobile channel conditions on IEEE 802.20,” Accepted in ICCET 2009.
VLSI Implementation of Signal Processing and Communication Systems
Algorithm-Architecture Co-Design
Architecture for Image Processing, Communication and Biomedical Applications
Low-Power and Reconfigurable Architecture
VLSI System Design
VLSI Testing
Reliability and Fault Tolerance
Design of High Performance Computational Block
Instructor, summer 2005, Shiraz University Research Center
Course: FPGA-based Digital System Design (FPGA Hardware, Verilog HDL, FPGA CAD Tools)
Instructor, summer 2005, Shiraz University Research Center
Course: Common Digital ICs and Their Applications
Teaching assistant, Fall 2008, University of Tehran
Undergraduate Course: VLSI system Design
Graduate Course: Advanced-VLSI system Design
Oct. 2006 – present: Research Assistant, Silicon Intelligence and VLSI Signal Processing Lab., School of ECE, University of Tehran, Tehran, Iran.
Sep. 2002 – July 2006: Research Assistant, Student Research Center of Shiraz University, Electrical Eng. Dep., University of Shiraz, Shiraz, Iran.
Course Presentations
“Fault Tolerant Implementation of Digital Signal Processing Systems,” Presentation in M.Sc. Seminar Course, University of Tehran, Feb. 2008.
“Wave Digital Filters with Minimum Multiplier for Discrete Hilbert Transformer Realization,” Presentation in DSP Course, University of Tehran, Jul. 2007.
“Digital Audio Broadcasting,” Presentation in Custom Implementation of DSP System Course, University of Tehran, June 2007.
“An asynchronous Array of Simple Processors for DSP Applications,” Presentation in Advanced VLSI Course, University of Tehran, Jul. 2006.
“Common-mode Feedback Techniques,” Presentation in Analog CMOS Integrated Circuit Design Course, University of Tehran, Jan. 2007.
Other Presentations
“Design flow for hardware implementation of digital filters,” Presentation in the forth international symposium on telecommunications, Tehran, Sep. 2008.
“Low cost concurrent error detection for lattice wave digital filters,” Presentation in the forth international symposium on telecommunications, Tehran, Sep. 2008.
“Fault Tolerant DSP,” Presentation in Silicon Intelligence and VLSI Signal Processing Lab., Oct. 2007.
“Concurrent Testing of DSP System,” Presentation in Silicon Intelligence and VLSI Signal Processing Lab., Dec. 2007.
“Reliable/fault-tolerant High Level Synthesis,” Presentation in Silicon Intelligence and VLSI Signal Processing Lab., Apr. 2008.
“Fault Effect on a sample IIR Filter,” Presentation in Silicon Intelligence and VLSI Signal Processing Lab., April. 2008.
“Frequency Domain Concurrent Fault Detection in DSP Systems,” Presentation in Silicon Intelligence and VLSI Signal Processing Lab., Jul. 2008.
“Automatic floating-point to fixed-point tools for DSP applications,” Presentation in Silicon Intelligence and VLSI Signal Processing Lab., Oct. 2007.
Persian (Native)
English (Fluent)
Arabic (Familiar)