Shervin Vakili (CV)
M.Sc., Computer Engineering – Architecture Design
School of Electrical and Computer Engineering
University of Tehran, Tehran 14395-515, Iran
Welcome
These web pages belong to Shervin Vakili and contain his educational and research works including publication, presentations and projects.
Short Biography
Shervin Vakili was born in 1984 in Tehran, Iran. He received the B.Sc. and M.Sc. degree in Computer Engineering from Iran University of Science and Technology and University of Tehran in 2006 and 2009, respectively. He has joined the Silicon Intelligence and VLSI Signal Processing Lab since Sep. 2007. He is currently working on design of novel and high performance MPSoC architectures under supervision of Dr. Sied Mehdi Fakhraie and Dr. Siamak Mohammadi.
Research Interests
His research interests include Multiprocessor System-on-Chip (MPSoC) design, reconfigurable hardware architectures, bio-inspired computing architectures, and hardware architectures for pattern recognition algorithms.
Theses
B.Sc. Thesis:
Title: Design and Implementation of a Hardware Accelerator for Hidden Markov Model
Algorithm
Description: This thesis consists of three main sections. First section studies HMM algorithm
and its computational requirements. Second section explores hardware design
space to find an efficient architectural approach to realize this algorithm as a
hardware core. Finally, the thesis proposes an architecture as a hardware
accelerator for HMM computations based on results of Section 2 and presents
its implementation results on FPGA.
M.Sc. Thesis:
Title: Design and Implementation of an NoC-Based Scalable Cellular Architecture Supervisors: Dr. Sied Mehdi Fakhraie and Dr. siamak Mohammadi
Description: This thesis presents a novel MPSoC system, which tries to overcome some of
these challenges using new architectural techniques. The main novelty of this
system is utilization of a hardware evolutionary core in its architecture to
perform two necessary activities for concurrent execution, at run-time. These
activities include decomposition of the program into tasks and scheduling them
among cooperative processors in the system. [Abstract][Defence Slides]
