مقالات علمی چاپ شده در مجلات

1. "Localizing Multiple Bugs in RTL Designs by Classifying Hit-statements using Neural Networks"
   Mahsa Heidari, Bijan Alizadehmalafeh
   IEEE TRANSACTIONS ON COMPUTERS, Vol. 74, No 5, pp.1786-1799, 2025
2. "AILIS: effective hardware accelerator for incremental learning with intelligent selection in classification"
   Nafiseh HosseinpourFardi, Bijan Alizadehmalafeh
   JOURNAL OF SUPERCOMPUTING, Vol. 81, No 4, pp.1-30, 2025
3. "Automatic Correction of Arithmetic Circuits in the Presence of Multiple Bugs by Groebner Basis Modification"
   Negar Aghapour Sabbagh, Bijan Alizadehmalafeh
   ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, Vol. 29, No 5, 2024
4. "Concealing Exposed Circuit Features Through a MaxSAT-Based Logic Locking Method"
   Mohammad Moradi Shahmiri, Bijan Alizadehmalafeh
   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 71, No 4, pp.1-1, 2024
5. "Systematic Trojan Detection in Crypto-Systems using the Model Checker"
   Hamed Hosseintalaee, Ali Jahanian, Bijan Alizadehmalafeh
   JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol. 33, No 3, 2024
6. "An FPGA-based Hardware Architecture for P+M class PMU using Accuracy-aware O-spline Filter Selection and Modulation Detection"
   Ali Falahati, Mahdieh Shamirzaei, Bijan Alizadehmalafeh
   IEEE Transactions on Instrumentation and Measurement, Vol. 73, 2024
7. "HyLock: Hybrid Logic Locking Based on Structural Fuzzing for Resisting Learning-based Attacks"
   Mohammad Moradi, Bijan Alizadehmalafeh
   The ISC International Journal of Information Security (ISeCure)), Vol. 15, No 3, pp.1-7, 2023
8. "DC-PUF: Machine Learning-Resistant PUF-Based Authentication Protocol Using Dependency Chain for Resource-Constraint IoT Devices"
   Abolfazl Sajady, Ahmad Shabani, Bijan Alizadehmalafeh
   JOURNAL OF NETWORK AND COMPUTER APPLICATIONS, Vol. 217, No 8, 2023
9. "Automatic Correction of RTL Designs using A Lightweight Partial High Level Synthesis"
   Bijan Alizadehmalafeh, Masoud Shiroei
   INTEGRATION-THE VLSI JOURNAL, Vol. 91, No 7, pp.173-181, 2023
10. "Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Mechanism for Resource-Constrained IoT Devices"
    Amir Ashtari, Ahmad Shabani, Bijan Alizadehmalafeh
    ISeCure-ISC International Journal of Information Security, Vol. 14, No 3, pp.1-8, 2022
11. "A Comparative Study of Machine Learning Classifiers for Secure RF-PUF-Based Authentication in Internet of Things"
    amir Ashtari, ahmad Shabani, Bijan Alizadehmalafeh
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 93, No 1, 2022
12. "Hardware Patching Methodology for Neutralizing Timing Hardware Trojans Using Vulnerability Analysis and Time Borrowing Scheme"
    Fatemeh Khormizi, Ahmad Shabani, Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 1, No 1, pp.1-1, 2022
13. "SAT-Based Integrated Hardware Trojan Detection and Localization Approach Through Path-Delay Analysis"
    Mohammad Sabri, Ahmad Shabani, Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 68, No 5, 2021
14. "Enhancing Hardware Trojan Detection Sensitivity Using Partition-Based Shuffling Scheme"
    Ahmad Shabani, Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 1, No 1, 2020
15. "AIOSC: Analytical Integer Word-length Optimization Based on System Characteristics for Recursive Fixed-Point Linear Time Invariant Systems"
    Mahdieh Grailoo Tanha, Bijan Alizadehmalafeh
    International Journal of Engineering, Vol. 33, No 7, pp.1223-1230, 2020
16. "PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices"
    Ahmad Shabani, Bijan Alizadehmalafeh
    JOURNAL OF NETWORK AND COMPUTER APPLICATIONS, Vol. 167, No 1, 2020
17. "Incremental SAT-based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits"
    Bijan Alizadehmalafeh, Yasaman Abadi
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 67, No 6, 2020
18. "PMTP: A MAX-SAT-Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability"
    Ahmad Shabani, Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 39, No 1, pp.25-33, 2020
19. "FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network"
    Ali Azarmi, Mohammad Emad, Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 67, No 4, 2019
20. "Data-path aware high-level ECO synthesis"
    Masoud Shiroie, Bijan Alizadehmalafeh, masahiro Fujita
    INTEGRATION-THE VLSI JOURNAL, Vol. 65, No 1, pp.88-96, 2019
21. "Combinational Hybrid Signal Selection with Updated Reachability Lists for Post-Silicon Debug"
    Siamack Beigmohammadi, Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 11, No 1, 2019
22. "QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations"
    Bijan Alizadehmalafeh, Mehdi Shakeri
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol. 65, No 12, pp.4326-4335, 2018
23. "FPGA-Based Implementation of a Novel Method for Estimating the Brillouin Frequency Shift in BOTDA and BOTDR Sensors"
    Mojtaba Abbasnejad, Bijan Alizadehmalafeh
    IEEE SENSORS JOURNAL, Vol. 18, No 5, pp.2015-2022, 2018
24. "Automatic Correction of Dynamic Power Management Architecture in Modern Processors"
    Reza Sharafinejad, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 26, No 2, 2018
25. "Incremental SAT-based Accurate Auto-correction of Sequential Circuits through Automatic Test Pattern Generation"
    Bijan Alizadehmalafeh, Reza Sharafinejad
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 18, No 5, pp.1-1, 2018
26. "A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs"
    Mehrnaz Ahmady, Sahand Salamat, Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 27, No 3, pp.1-4, 2018
27. "Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors"
    Fatemeh Refan, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 18, No 6, pp.1-9, 2018
28. "FPGA-Based Implementation of an Artificial Neural Network for Measurement Acceleration in BOTDA Sensors"
    Mojtaba Abbasnejad, Bijan Alizadehmalafeh
    IEEE Transactions on Instrumentation and Measurement, Vol. 68, No 5, pp.1-9, 2018
29. "A Resource-limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications"
    Shayan Moeini, Bijan Alizadehmalafeh, Mohammad Emad, Reza Ebrahimpour
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 64, No 10, pp.1217-1222, 2017
30. "Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors"
    Fatemeh Refan, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 25, No 7, pp.2059-2070, 2017
31. "Systematic Design Space Exploration of Floating Point Expressions on FPGA"
    Alireza Mahzoon, Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 64, No 3, pp.274-278, 2017
32. "Accuracy-Aware Enhanced Range Analysis in Fixed-Point Polynomial Data-Path"
    Mahdieh Grailoo, Bijan Alizadehmalafeh, Behjat Forouzandeh
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. pp, No 99, pp.1-1, 2017
33. "OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs with Optimized Exponent/Mantissa Widths"
    Alireza Mahzoon, Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 25, No 1, pp.198-209, 2017
34. "Scalable SMT-based Equivalence Checking of Nested Loop Pipelining in Behavioral Synthesis"
    Mohammad Reza Azarbad, Bijan Alizadehmalafeh
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, Vol. 22, No 2, 2016
35. "A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the presence of Variations"
    Mehrnaz Ahmadi, Bijan Alizadehmalafeh, Behjat Forouzandeh
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol. 1, No 1, pp.111-120, 2016
36. "Genetic Algorithm Based FPGA Architectural Exploration using Analytical Models"
    Hossein Mehri, Bijan Alizadehmalafeh
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, Vol. 22, No 1, 2016
37. "UAFEA: Unified Analytical Framework for IA/AA-based Error Analysis of Fixed-Point Polynomial Specifications"
    Mahdieh Graeilo, Bijan Alizadehmalafeh, Behjat Forouzandeh
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 20, No 6, pp.220-226, 2016
38. "A dynamic specification to automatically debug and correct various divider circuits"
    Hashem Haghbayan, Bijan Alizadehmalafeh
    INTEGRATION-THE VLSI JOURNAL, Vol. 53, No 2016, pp.100-114, 2016
39. "Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance"
    Mehrzad Nejat, Bijan Alizadehmalafeh, Ali Afzali Kousha
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 1, No 1, pp.1-1, 2015
40. "Analytical performance model for FPGA-based reconfigurable computing"
    Hossein Mehri, Bijan Alizadehmalafeh
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 39, No 8, pp.796-806, 2015
41. "Automatic High-level Data-flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition"
    Samaneh Ghandali, Bijan Alizadehmalafeh, ماساهیرو فوجیتا, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON COMPUTERS, Vol. 64, No 6, pp.1579-1593, 2015
42. "A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs"
    Bijan Alizadehmalafeh, Payman Behnam, Somayeh Sadeghi
    IEEE TRANSACTIONS ON COMPUTERS, Vol. 64, No 6, pp.1564-1578, 2015
43. "Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction"
    Farimah Farahmandi, Bijan Alizadehmalafeh
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 2, No 39, pp.83-96, 2015
44. "Formal Equivalence Verification and Debugging Techniques with Auto-correction Mechanism for RTL Designs"
    Bijan Alizadehmalafeh, Payman Behnam
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 37, pp.1108-1121, 2013
45. "Formal Verification and Debugging of Precise Interrupts on High Performance Microprocessors"
    Bijan Alizadehmalafeh
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, Vol. 17, No 4, pp.1-8, 2012
46. "A New Approach for Automatic Test Pattern Generation in Register transfer Level Circuits"
    محمد میرزائی, Mahmoud Tabandeh , Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE DESIGN & TEST OF COMPUTERS, Vol. -, No 99, 2012
47. "Modular Data - path Optimization and Verification Based on Modular - HED"
    Bijan Alizadehmalafeh, Masahiro Fujita
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 29, No 9, pp.1422-1435, 2010
48. "Coverage Driven High Level Test Generation using a Polynomial Model of Sequential Circuits"
    Bijan Alizadehmalafeh, Mohammad Mirzaei , Masahiro Fujita
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 29, No 5, pp.737-748, 2010
49. "A Formal Approach for Debugging Arithmetic Circuits"
    Omid Sarbishei , Mahmoud Tabandeh , Bijan Alizadehmalafeh, Masahiro Fujita
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 28, No 5, pp.742-754, 2009
50. "A Unified Framework for Equivalence Verification of Datapath Oriented Applications"
    Bijan Alizadehmalafeh, Masahiro Fujita
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Vol. 92, No 5, pp.985-994, 2009
51. "اSQ-PUF: پروتکل احراز هویت مبتنی برPUF مقاوم در برابر حملات یادگیری ماشین"
    سید ابوالفضل سجادی هزاوه، بیژن علیزاده ملفه
    نشریه مهندسی برق و مهندسی کامپیوتر ایران، نسخه 21، شماره 3، 1402
52. "آنالیز آسیب پذیری مدارهای دیجیتال در برابر تروجان سخت افزار زمانی مبتنی بر عملگر خازنی"
    فاطمه خورمیزی، بیژن علیزاده ملفه
    امنیت فضای تولید و تبادل اطلاعات (منادی)، نسخه 20، شماره 1، صفحات:18-25، 1401
53. "درستی سنجی صوری معماری مدیریت توان در سطح سیستم برای پردازنده های مدرن"
    سیدرضا شرفی نژاد، بیژن علیزاده ملفه
    مهندسی برق و الکترونیک ایران، نسخه 18، شماره 4، 1400
54. "مدل عملکردی تحلیلی FPGA برای پردازش با قابلیت پیکربندی مجدد"
    حسین مهری، بیژن علیزاده ملفه
    انجمن مهندسین برق-الکترونیک ایران، نسخه 13، شماره 4، صفحات:1-13، 1395

مقالات علمی ارائه شده در همایش‌ها

1. "Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Machanism for Resource-Constrained IoT Devices"
   Amir Ashtari, Ahmad Shabani, Bijan Alizadehmalafeh
   19th International ISC Conference on Information Security and Cryptology (ISCISC’2022), 2022
2. "Arithmetic Circuit Correction by Adding Optimized Correctors Based on Groebner Basis Computation"
   Negar Aghapour Sabbagh, Bijan Alizadehmalafeh
   26th IEEE European Test Symposium, 2021
3. "ACPA: Exploiting Approximate Computing for High-Level Imprecision Optimization of Fixed-point LTI systems"
   Mahdieh Grailoo Tanha, Bijan Alizadehmalafeh, Tooraj Nikoubin
   14th IEEE Dallas Circuits and Systems Conference, 2020
4. "Formal Verification of Non-Functional Strategies of System-Level Power Management Architecture in Modern Processors"
   Seyyed Reza Sharafinezhad, Bijan Alizadehmalafeh, Tooraj Nikoubin
   14th IEEE Dallas Circuits and System Conference, 2020
5. "A New RF-PUF Based Authentication of Internet of Things Using Random Forest Classification"
   Amir Ashtari, Ahmad Shabani, Bijan Alizadehmalafeh
   2019 16th International ISC (Iranian Society of Cryptology) Conference on Information Security and Cryptology (ISCISC), 2019
6. "High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization"
   Sahand Salamat, Mohammadreza Azarbad, Bijan Alizadehmalafeh
   IEEE International Conference on Rebooting Computing, 2018
7. "Reducing Search Space for Fault Diagnosis: A Probability-based Scoring Approach"
   حسین صباغیان بیدگلی , Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
   ISVLSI 2017, 2017
8. "Systematic Approximate Logic Optimization Using Don’t Care Conditions"
   Sahand Salamat, Mehrnaz Ahmadi, Bijan Alizadehmalafeh, Masahiro Fujita
   ISQED, 2017
9. "Combinational Trace Signal Selection with Improved State Restoration for Post-Silicon Debug"
   Siamack Beigmohammadi, Bijan Alizadehmalafeh
   DATE 2016, 2016
10. "Formally Analyzing Fault Tolerance in Datapath Designs using Equivalence Checking"
    Payman Behnam, Bijan Alizadehmalafeh, Sajjad Taheri, ماساهیرو فوجیتا
    ASPDAC 2016, 2016
11. "In-circuit Mutation-based Automatic Correction of Certain Design Errors Using SAT Mechanisms"
    Payman Behnam, Bijan Alizadehmalafeh
    ATS 2015, 2015
12. "Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization"
    Alireza Mahzoon, Bijan Alizadehmalafeh
    ISVLSI 2015, 2015
13. "A Timing Error Mitigation Technique for High Performance Designs"
    Mehrnaz Ahmadi, Bijan Alizadehmalafeh, Behjat Forouzandeh
    ISVLSI 2015, 2015
14. "Signature Oriented Model Pruning to Facilitate Multi-Threaded Processors Debugging"
    Fatemeh Refan, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE VLSI Test Symposium (VTS 2015), 2015
15. "UPF-based formal verification of low power techniques in modern processors"
    Reza Sharafinejad, Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    IEEE VLSI Test Symposium (VTS 2015), 2015
16. "Low Power Scheduling in High-level Synthesis using Dual-Vth Library"
    Samaneh Ghandali, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ISQED 2015, 2015
17. "Automated formal approach for debugging dividers using dynamic specification"
    Mohammad Hashem Haghbayan, Bijan Alizadehmalafeh, Amir Rahmani, Pasi Liljeberg, Hannu Tenhunnen
    IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, 2014
18. "Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits"
    Farimah Farahmandi, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ISVLSI 2014, 2014
19. "A low-power enhanced bitmask-dictionary scheme for test data compression"
    Vahid Janfaza, Payman Behnam, Behjat Forouzandeh, Bijan Alizadehmalafeh
    ISVLSI 2014, 2014
20. "Improving Polynomial Datapath Debugging with HEDs"
    Somayeh Sadeghi, Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi, Masahiro Fujita
    ETS 2014 (European Test Symposium), 2014
21. "Automatic Correction of Certain Design Errors Using Mutation Technique"
    Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ETS 2014 (European Test Symposium), 2014
22. "An analytical dynamic and leakage power model for FPGAs"
    Hossein Mehri, Bijan Alizadehmalafeh
    ICEE 2014, 2014
23. "Dynamic Flip-Flop conversion to tolerate process variation in low power circuits"
    Mehrzad Nejat, Ali Afzali Kousha, Bijan Alizadehmalafeh
    Design Automation and Test in Europe, 2014
24. "RTL Datapath Optimization using System-level Transformations"
    Samaneh Ghandali, Bijan Alizadehmalafeh, Masahiro Fujita, Zainalabedin Navabi Shirazi
    ISQED, 2014
25. "RTL Datapath Optimization Using System Level Transformations"
    Samaneh Ghandali, Bijan Alizadehmalafeh, Masahiro Fujita, Zainalabedin Navabi Shirazi
    ISQED, 2014
26. "Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism"
    Hashem Haghbayan, Bijan Alizadehmalafeh, Payman Behnam, Saeed Safari
    VLSI Design, 2014
27. "A Probabilistic Approach for Counterexample Generation to Aid Design Debugging"
    Payman Behnam, Hossein Sabaghian, Bijan Alizadehmalafeh, Kamyar Mohajerani, Zainalabedin Navabi Shirazi
    EWDTS 2013, 2013
28. "An Analytical Dynamic and Leakage Power Model for FPGAs"
    Hossein Mehri, Bijan Alizadehmalafeh
    International Symposium on VLSI, 2013
29. "Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits"
    Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    International Symposium VLSI, 2013
30. "Mutation-based Technique for Automatic Correction of Functional Bugs in Digital Designs"
    Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    International Symposium on VLSI, 2013
31. "A Functional Test Generation Technique for RTL Datapaths"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    High Level Design Validation and Test Workshop, 2012
32. "Mutation Based Debugging Technique with Auto-Correction Mechanism for RTL Designs"
    Bijan Alizadehmalafeh, پیمان بهنام, Zainalabedin Navabi Shirazi, ماساهیرو فوجیتا
    IEEE International Workshop on Silicon Debug and Diagnosis, 2012
33. "Polynomial Datapath Synthesis and Optimization Based on Vanishing Polynomial over Z(2m and Algebraic Techniques"
    Bijan Alizadehmalafeh, سمانه قندالی, Zainalabedin Navabi Shirazi, ماساهیرو فوجیتا
    International Conference on Formal Methods and Models for Co-design, 2012
34. "A Formal Approach to Debug Polynomial Datapath Designs"
    Bijan Alizadehmalafeh
    Asia and South Pacific Design Automation Conference, 2012
35. "Modular Equivalence Verification of Polynomial Datapaths with multiple word length operands"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    High Level Design Validation and Test, 2011
36. "A Symbolic Model-based Diagnosis with Auto-correction Framework for Arithmetic Circuits"
    Bijan Alizadehmalafeh
    Asia Symposium on Quality Electronic Design, 2011
37. "Early Case-splitting and False Path Detection to Improve High Level ATPG Techniques"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    International Symposium on Circuits and Systems, 2011
38. "Pipelined Microprocessors Optimization and Debugging"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    International Symposium on Applied Reconfigurable Computing, 2011
39. "Debugging and Optimizing High Performance Superscalar Out-of-Order Processors Using Formal Verification Techniques"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    International Symposium on Quality Electronic Design, 2011
40. "A Debugging Method for Repairing Post-Silicon Bugs of High Performance Processors in the Fields"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    International Conference on Field Programmable Technology, 2010
41. "Polynomial datapath optimization using constraint solving and formal modeling"
    Bijan Alizadehmalafeh, فری هایدیک, گورشین فی, ماساهیرو فوجیتا, رولف دسلر
    International Conference on Computer Aided Design, 2010
42. "Aggressive Over-clocking Support using a Novel Timing Error Recovery Technique on FPGAs"
    Bijan Alizadehmalafeh, امیرمسعود قره باغی, ماساهیرو فوجیتا
    Symposium on FPGA, 2010
43. "Guided Gate-level ATPG for Sequential Circuits using a High-level Test Generation Approach"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    Asia and South Pacific Design Automation Conference, 2010
44. "Optimization of Modular Multiplication on FPGA using Dont Care Conditions"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    International Conference on Field Programmable Technology, 2009
45. "Modular Arithmetic Decision Procedure with Auto-correction Mechanism"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    High level design validation and test, 2009
46. "Polynomial Data-path Optimization using Partitioning and Compensation Heuristics"
    Bijan Alizadehmalafeh, امید سربیشه ای, ماساهیرو فوجیتا
    Design Automation Conference (DAC, 2009
47. "High-level Optimization of Integer Multipliers over a Finite Bit-width with Verification Capabilities"
    Bijan Alizadehmalafeh, امید سربیشه ای, محمود تابنده, ماساهیرو فوجیتا
    International Conference on Formal Methods and Models for Codesign, 2009
48. "آنالیز آسیب پذیری مدارهای دیجیتال در برابر تروجان سخت افزار زمانی مبتنی بر عملگر خازنی"
    فاطمه خورمیزی، بیژن علیزاده ملفه
    18 امین کنفرانس بین المللی انجمن رمز ایران، 1400