مقالات علمی چاپ شده در مجلات

1. "HyLock: Hybrid Logic Locking Based on Structural Fuzzing for Resisting Learning-based Attacks"
   Bijan Alizadehmalafeh, Mohammad Moradi
   The ISC International Journal of Information Security (ISeCure)), Vol. 15, No 3, pp.1-7, 0036
2. "Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Mechanism for Resource-Constrained IoT Devices"
   Bijan Alizadehmalafeh, Ahmad Shabani, Amir Ashtari
   ISeCure-ISC International Journal of Information Security, Vol. 14, No 3, pp.1-8, 0036
3. "Enhancing Hardware Trojan Detection Sensitivity Using Partition-Based Shuffling Scheme"
   Ahmad Shabani, Bijan Alizadehmalafeh
   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 1, No 1, 0029
4. "AIOSC: Analytical Integer Word-length Optimization Based on System Characteristics for Recursive Fixed-Point Linear Time Invariant Systems"
   Bijan Alizadehmalafeh, Mahdieh Grailoo Tanha
   International Journal of Engineering, Vol. 33, No 7, pp.1223-1230, 0028
5. "Automatic Correction of RTL Designs using A Lightweight Partial High Level Synthesis"
   Bijan Alizadehmalafeh, Masoud Shiroei
   INTEGRATION-THE VLSI JOURNAL, Vol. 91, No 7, pp.173-181, 0027
6. "FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network"
   Bijan Alizadehmalafeh, Mohammad Emad, Ali Azarmi
   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 67, No 4, 0026
7. "A Resource-limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications"
   Reza Ebrahimpour, Mohammad Emad, Bijan Alizadehmalafeh, Shayan Moeini
   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 64, No 10, pp.1217-1222, 0026
8. "Hardware Patching Methodology for Neutralizing Timing Hardware Trojans Using Vulnerability Analysis and Time Borrowing Scheme"
   Bijan Alizadehmalafeh, Ahmad Shabani, Fatemeh Khormizi
   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 1, No 1, pp.1-1, 0023
9. "SAT-Based Integrated Hardware Trojan Detection and Localization Approach Through Path-Delay Analysis"
   Bijan Alizadehmalafeh, Ahmad Shabani, Mohammad Sabri
   IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 68, No 5, 0020
10. "A Comparative Study of Machine Learning Classifiers for Secure RF-PUF-Based Authentication in Internet of Things"
    Bijan Alizadehmalafeh, ahmad Shabani, amir Ashtari
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 93, No 1, 0020
11. "Incremental SAT-based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits"
    Yasaman Abadi, Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 67, No 6, 0015
12. "An FPGA-based Hardware Architecture for P+M class PMU using Accuracy-aware O-spline Filter Selection and Modulation Detection"
    Bijan Alizadehmalafeh, Mahdieh Shamirzaei, Ali Falahati
    IEEE Transactions on Instrumentation and Measurement, Vol. 73, 0013
13. "QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations"
    Bijan Alizadehmalafeh, Mehdi Shakeri
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, Vol. 65, No 12, pp.4326-4335, 0007
14. "Analytical performance model for FPGA-based reconfigurable computing"
    Bijan Alizadehmalafeh, Hossein Mehri
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 39, No 8, pp.796-806, 0007
15. "DC-PUF: Machine Learning-Resistant PUF-Based Authentication Protocol Using Dependency Chain for Resource-Constraint IoT Devices"
    Bijan Alizadehmalafeh, Ahmad Shabani, Abolfazl Sajady
    JOURNAL OF NETWORK AND COMPUTER APPLICATIONS, Vol. 217, No 8, 0007
16. "Concealing Exposed Circuit Features Through a MaxSAT-Based Logic Locking Method"
    Bijan Alizadehmalafeh, Mohammad Moradi Shahmiri
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, Vol. 71, No 4, pp.1-1, 0006
17. "PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices"
    Bijan Alizadehmalafeh, Ahmad Shabani
    JOURNAL OF NETWORK AND COMPUTER APPLICATIONS, Vol. 167, No 1, 0006
18. "Combinational Hybrid Signal Selection with Updated Reachability Lists for Post-Silicon Debug"
    Bijan Alizadehmalafeh, Siamack Beigmohammadi
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 11, No 1, 0006
19. "Data-path aware high-level ECO synthesis"
    masahiro Fujita, Bijan Alizadehmalafeh, Masoud Shiroie
    INTEGRATION-THE VLSI JOURNAL, Vol. 65, No 1, pp.88-96, 0006
20. "Systematic Trojan Detection in Crypto-Systems using the Model Checker"
    Bijan Alizadehmalafeh, Ali Jahanian, Hamed Hosseintalaee
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol. 33, No 3, 0006
21. "PMTP: A MAX-SAT-Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability"
    Bijan Alizadehmalafeh, Ahmad Shabani
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 39, No 1, pp.25-33, 0006
22. "A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs"
    Bijan Alizadehmalafeh, Sahand Salamat, Mehrnaz Ahmady
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 27, No 3, pp.1-4, 0006
23. "Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors"
    Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi, Fatemeh Refan
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 18, No 6, pp.1-9, 0006
24. "Incremental SAT-based Accurate Auto-correction of Sequential Circuits through Automatic Test Pattern Generation"
    Bijan Alizadehmalafeh, Reza Sharafinejad
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 18, No 5, pp.1-1, 0006
25. "FPGA-Based Implementation of an Artificial Neural Network for Measurement Acceleration in BOTDA Sensors"
    Bijan Alizadehmalafeh, Mojtaba Abbasnejad
    IEEE Transactions on Instrumentation and Measurement, Vol. 68, No 5, pp.1-9, 0006
26. "Coverage Driven High Level Test Generation using a Polynomial Model of Sequential Circuits"
    Masahiro Fujita , Mohammad Mirzaei , Bijan Alizadehmalafeh
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 29, No 5, pp.737-748, 0006
27. "A Unified Framework for Equivalence Verification of Datapath Oriented Applications"
    Masahiro Fujita , Bijan Alizadehmalafeh
    IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, Vol. 92, No 5, pp.985-994, 0006
28. "درستی سنجی صوری معماری مدیریت توان در سطح سیستم برای پردازنده های مدرن"
    بیژن علیزاده ملفه، سیدرضا شرفی نژاد
    مهندسی برق و الکترونیک ایران، نسخه 18، شماره 4، -593
29. "اSQ-PUF: پروتکل احراز هویت مبتنی برPUF مقاوم در برابر حملات یادگیری ماشین"
    بیژن علیزاده ملفه، سید ابوالفضل سجادی هزاوه
    نشریه مهندسی برق و مهندسی کامپیوتر ایران، نسخه 21، شماره 3، -594
30. "آنالیز آسیب‌پذیری مدارهای دیجیتال در برابر تروجان سخت‌افزار زمانی مبتنی بر عملگر خازنی"
    بیژن علیزاده ملفه، فاطمه خورمیزی
    امنیت فضای تولید و تبادل اطلاعات (منادی)، نسخه 20، شماره 1، صفحات:18-25، -604

مقالات علمی ارائه شده در همایش‌ها

1. "Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Machanism for Resource-Constrained IoT Devices"
   Bijan Alizadehmalafeh, Ahmad Shabani, Amir Ashtari
   19th International ISC Conference on Information Security and Cryptology (ISCISC’2022), 2022
2. "Arithmetic Circuit Correction by Adding Optimized Correctors Based on Groebner Basis Computation"
   Bijan Alizadehmalafeh, Negar Aghapour Sabbagh
   26th IEEE European Test Symposium, 2021
3. "ACPA: Exploiting Approximate Computing for High-Level Imprecision Optimization of Fixed-point LTI systems"
   Tooraj Nikoubin, Bijan Alizadehmalafeh, Mahdieh Grailoo Tanha
   14th IEEE Dallas Circuits and Systems Conference, 2020
4. "Formal Verification of Non-Functional Strategies of System-Level Power Management Architecture in Modern Processors"
   Tooraj Nikoubin, Bijan Alizadehmalafeh, Seyyed Reza Sharafinezhad
   14th IEEE Dallas Circuits and System Conference, 2020
5. "A New RF-PUF Based Authentication of Internet of Things Using Random Forest Classification"
   Bijan Alizadehmalafeh, Ahmad Shabani, Amir Ashtari
   2019 16th International ISC (Iranian Society of Cryptology) Conference on Information Security and Cryptology (ISCISC), 2019
6. "High-Level Synthesis of Non-Rectangular Multi-Dimensional Nested Loops Using Reshaping and Vectorization"
   Mohammadreza Azarbad, Sahand Salamat, Bijan Alizadehmalafeh
   IEEE International Conference on Rebooting Computing, 2018
7. "Reducing Search Space for Fault Diagnosis: A Probability-based Scoring Approach"
   Bijan Alizadehmalafeh, حسین صباغیان بیدگلی , Payman Behnam, Zainalabedin Navabi Shirazi
   ISVLSI 2017, 2017
8. "Systematic Approximate Logic Optimization Using Don’t Care Conditions"
   Sahand Salamat, Mehrnaz Ahmadi, Masahiro Fujita, Bijan Alizadehmalafeh
   ISQED, 2017
9. "Combinational Trace Signal Selection with Improved State Restoration for Post-Silicon Debug"
   Bijan Alizadehmalafeh, Siamack Beigmohammadi
   DATE 2016, 2016
10. "Formally Analyzing Fault Tolerance in Datapath Designs using Equivalence Checking"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا , Payman Behnam, Sajjad Taheri
    ASPDAC 2016, 2016
11. "In-circuit Mutation-based Automatic Correction of Certain Design Errors Using SAT Mechanisms"
    Bijan Alizadehmalafeh, Payman Behnam
    ATS 2015, 2015
12. "A Timing Error Mitigation Technique for High Performance Designs"
    Bijan Alizadehmalafeh, Behjat Forouzandeh, Mehrnaz Ahmadi
    ISVLSI 2015, 2015
13. "Multi-objective Optimization of Floating Point Arithmetic Expressions Using Iterative Factorization"
    Bijan Alizadehmalafeh, Alireza Mahzoon
    ISVLSI 2015, 2015
14. "HOFEX: High Level Optimization of Floating Point Expressions for Implementation on FPGAs"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا , Alireza Mahzoon
    IWLS 2015, 2015
15. "Signature Oriented Model Pruning to Facilitate Multi-Threaded Processors Debugging"
    Fatemeh Refan, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE VLSI Test Symposium (VTS 2015), 2015
16. "UPF-based formal verification of low power techniques in modern processors"
    Bijan Alizadehmalafeh, Reza Sharafinejad, ماساهیرو فوجیتا
    IEEE VLSI Test Symposium (VTS 2015), 2015
17. "Low Power Scheduling in High-level Synthesis using Dual-Vth Library"
    Zainalabedin Navabi Shirazi, Samaneh Ghandali, Bijan Alizadehmalafeh
    ISQED 2015, 2015
18. "Automated formal approach for debugging dividers using dynamic specification"
    Amir Rahmani, Hannu Tenhunnen, Bijan Alizadehmalafeh, Pasi Liljeberg, Mohammad Hashem Haghbayan
    IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2014, 2014
19. "A low-power enhanced bitmask-dictionary scheme for test data compression"
    Vahid Janfaza, Payman Behnam, Bijan Alizadehmalafeh, Behjat Forouzandeh
    ISVLSI 2014, 2014
20. "Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits"
    Farimah Farahmandi, Zainalabedin Navabi Shirazi, Bijan Alizadehmalafeh
    ISVLSI 2014, 2014
21. "Automatic Correction of Certain Design Errors Using Mutation Technique"
    Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ETS 2014 (European Test Symposium), 2014
22. "Improving Polynomial Datapath Debugging with HEDs"
    Somayeh Sadeghi, Bijan Alizadehmalafeh, Payman Behnam, Masahiro Fujita, Zainalabedin Navabi Shirazi
    ETS 2014 (European Test Symposium), 2014
23. "An analytical dynamic and leakage power model for FPGAs"
    Hossein Mehri, Bijan Alizadehmalafeh
    ICEE 2014, 2014
24. "Dynamic Flip-Flop conversion to tolerate process variation in low power circuits"
    Ali Afzali Kousha, Bijan Alizadehmalafeh, Mehrzad Nejat
    Design Automation and Test in Europe, 2014
25. "RTL Datapath Optimization using System-level Transformations"
    Samaneh Ghandali, Masahiro Fujita, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ISQED, 2014
26. "RTL Datapath Optimization Using System Level Transformations"
    Zainalabedin Navabi Shirazi, Bijan Alizadehmalafeh, Samaneh Ghandali, Masahiro Fujita
    ISQED, 2014
27. "Formal Verification and Debugging of Array Dividers with Auto-correction Mechanism"
    Hashem Haghbayan, Saeed Safari, Bijan Alizadehmalafeh, Payman Behnam
    VLSI Design, 2014
28. "A Probabilistic Approach for Counterexample Generation to Aid Design Debugging"
    Zainalabedin Navabi Shirazi, Hossein Sabaghian, Bijan Alizadehmalafeh, Payman Behnam, Kamyar Mohajerani
    EWDTS 2013, 2013
29. "Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits"
    Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    International Symposium VLSI, 2013
30. "Mutation-based Technique for Automatic Correction of Functional Bugs in Digital Designs"
    Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    International Symposium on VLSI, 2013
31. "An Analytical Dynamic and Leakage Power Model for FPGAs"
    Bijan Alizadehmalafeh, Hossein Mehri
    International Symposium on VLSI, 2013
32. "A Functional Test Generation Technique for RTL Datapaths"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    High Level Design Validation and Test Workshop, 2012
33. "Mutation Based Debugging Technique with Auto-Correction Mechanism for RTL Designs"
    Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi, ماساهیرو فوجیتا, پیمان بهنام
    IEEE International Workshop on Silicon Debug and Diagnosis, 2012
34. "Polynomial Datapath Synthesis and Optimization Based on Vanishing Polynomial over Z(2m and Algebraic Techniques"
    Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi, ماساهیرو فوجیتا, سمانه قندالی
    International Conference on Formal Methods and Models for Co-design, 2012
35. "A Formal Approach to Debug Polynomial Datapath Designs"
    Bijan Alizadehmalafeh
    Asia and South Pacific Design Automation Conference, 2012
36. "Modular Equivalence Verification of Polynomial Datapaths with multiple word length operands"
    ماساهیرو فوجیتا, Bijan Alizadehmalafeh
    High Level Design Validation and Test, 2011
37. "A Symbolic Model-based Diagnosis with Auto-correction Framework for Arithmetic Circuits"
    Bijan Alizadehmalafeh
    Asia Symposium on Quality Electronic Design, 2011
38. "Early Case-splitting and False Path Detection to Improve High Level ATPG Techniques"
    ماساهیرو فوجیتا, Bijan Alizadehmalafeh
    International Symposium on Circuits and Systems, 2011
39. "Pipelined Microprocessors Optimization and Debugging"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    International Symposium on Applied Reconfigurable Computing, 2011
40. "Debugging and Optimizing High Performance Superscalar Out-of-Order Processors Using Formal Verification Techniques"
    ماساهیرو فوجیتا, Bijan Alizadehmalafeh
    International Symposium on Quality Electronic Design, 2011
41. "Post-silicon Debugging with High Level Design Descriptions and Programmable Controllers"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا, هیروکی یوشیدا, تو ماتسوموتو
    Microprocessor Test and Verification, 2010
42. "A Debugging Method for Repairing Post-Silicon Bugs of High Performance Processors in the Fields"
    ماساهیرو فوجیتا, Bijan Alizadehmalafeh
    International Conference on Field Programmable Technology, 2010
43. "Polynomial datapath optimization using constraint solving and formal modeling"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا, رولف دسلر, گورشین فی, فری هایدیک
    International Conference on Computer Aided Design, 2010
44. "Aggressive Over-clocking Support using a Novel Timing Error Recovery Technique on FPGAs"
    Bijan Alizadehmalafeh, امیرمسعود قره باغی, ماساهیرو فوجیتا
    Symposium on FPGA, 2010
45. "Guided Gate-level ATPG for Sequential Circuits using a High-level Test Generation Approach"
    ماساهیرو فوجیتا, Bijan Alizadehmalafeh
    Asia and South Pacific Design Automation Conference, 2010
46. "Optimization of Modular Multiplication on FPGA using Dont Care Conditions"
    ماساهیرو فوجیتا, Bijan Alizadehmalafeh
    International Conference on Field Programmable Technology, 2009
47. "Optimization of Modular Multiplication on FPGA Using Don’t Care Conditions"
    Masahiro Fujita, Bijan Alizadehmalafeh
    ICFPT, 2009
48. "Modular Arithmetic Decision Procedure with Auto-correction Mechanism"
    ماساهیرو فوجیتا, Bijan Alizadehmalafeh
    High level design validation and test, 2009
49. "Improved Heuristics for Finite Word-Length Polynomial Data-path Optimization"
    ماساهیرو فوجیتا, Bijan Alizadehmalafeh
    International Conference on Computer Aided Design, 2009
50. "Improved Heuristics for Finite Word-Length Polynomial Datapath Optimization"
    Bijan Alizadehmalafeh, Masahiro Fujita
    ICCAD, 2009
51. "Polynomial Data-path Optimization using Partitioning and Compensation Heuristics"
    ماساهیرو فوجیتا, امید سربیشه ای, Bijan Alizadehmalafeh
    Design Automation Conference (DAC, 2009
52. "High-level Optimization of Integer Multipliers over a Finite Bit-width with Verification Capabilities"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا, امید سربیشه ای, محمود تابنده
    International Conference on Formal Methods and Models for Codesign, 2009
53. "A Debug Methodology for Arithmetic Circuits based on Horner Decision Diagrams"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا, امید سربیشه ای
    Constraints in Formal Verification, 2009
54. "Modularity in Word-level Decision Diagrams"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    Reed Muller Workshop, 2009
55. "Modular-HED: A Canonical Decision Diagram for Modular Equivalence Verification of Polynomial Functions"
    ماساهیرو فوجیتا, Bijan Alizadehmalafeh
    Constraints in Formal Verification, 2008
56. "Arithmetic Circuits Verification without Looking for Internal Equivalences"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا, امید سربیشه ای
    International Conference on Formal Methods and Models for Codesign, 2008
57. "System-level Implementation of DSP Applications on FPGA"
    Bijan Alizadehmalafeh, محمود ممتازپور, محمود تابنده
    Computer Society of Iran Computer Conference, 2008
58. "Sequential Equivalence Checking using a Hybrid Boolean-Word Level Decision Diagram"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    Computer Society of Iran Computer Conference, 2008
59. "A Novel Formal Approach to Generate High-level Test Vectors without ILP and SAT Solvers"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    High level design validation and test, 2007
60. "Automatic Merge-point Detection for Sequential Equivalence Checking of System-level and RTL Descriptions"
    ماساهیرو فوجیتا, Bijan Alizadehmalafeh
    International Conference on Automated Technology for Verification and Analysis, 2007
61. "Simulation and Improvement of Two Digital Adaptive Frequency Calibration Techniques for Fast Locking Wide-Band Frequency Synthesizers"
    Bijan Alizadehmalafeh, محمود ممتازپور, محمدرضا سعادت
    Design and technology of integrated systems in nanoscale era, 2007
62. "LTED: A Canonical and Compact Hybrid Word-Boolean Representation as a Formal Model for Hardware/Software Co-designs"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    Constraints in Formal Verification, 2007
63. "A Hybrid Approach for Equivalence Checking between System Level and RTL Descriptions"
    Bijan Alizadehmalafeh, ماساهیرو فوجیتا
    International Workshop on Logic and Synthesis, 2007
64. "Word Level Functional Coverage Computation"
    Bijan Alizadehmalafeh
    Asia and South Pacific Design Automation Conference, 2006
65. "Binary Taylor Diagrams: An Efficient Implementation of Taylor Expansion Diagrams"
    Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi, شمشیری, علی علی صفایی, داود نادری قمی, پژمان لطفی کامران
    ISCAS, 2005
66. "Using Integer Equations for High Level Formal Verification Property Checking"
    Bijan Alizadehmalafeh, محمدرضا کاکویی
    International Symposium on Quality Electronic Design, 2003
67. "آنالیز آسیب پذیری مدارهای دیجیتال در برابر تروجان سخت افزار زمانی مبتنی بر عملگر خازنی"
    بیژن علیزاده ملفه، فاطمه خورمیزی
    18 امین کنفرانس بین المللی انجمن رمز ایران، 1400