منو
زین العابدین نوابی شیرازی

استاد

تاریخ به‌روزرسانی: 1404/02/18

زین العابدین نوابی شیرازی

دانشکدگان ‌فنی / دانشکده مهندسی‌ برق‌ و کامپیوتر

مقالات علمی چاپ شده در مجلات

  1. "Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators"
    Alireza Nahvi, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 32, No 7, pp.1-12, 2024
  2. "Analysis and Enhancement of Resilience for LSTM Accelerators Using Residue-Based CEDs"
    Nooshin Nosrati, Zainalabedin Navabi Shirazi
    IEEE Access, Vol. 12, pp.52851-52866, 2024
  3. "An Efficient RTL Design for a Wearable Brain–Computer Interface"
    Tahereh Vasei, Mohammad Ali Saber, Alireza Nahvy, Zainalabedin Navabi Shirazi
    IET Computers and Digital Techniques, Vol. 2024, pp.1-15, 2024
  4. "LUT Input Reordering to Reduce Aging Impact on FPGA LUTs"
    Mohammad Ebrahimi, Rezgar Sadeghi, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON COMPUTERS, Vol. 69, No 10, pp.1500-1506, 2020
  5. "Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information"
    Mohammad Ebrahimi, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 39, No 10, 2020
  6. "Self-Adjusting Monitor for Measuring Aging Rate and Advancement"
    Somayeh Sadeghi Kohan, Mehdi Kamal, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, Vol. 8, No 3, 2020
  7. "Automatic Correction of Dynamic Power Management Architecture in Modern Processors"
    Reza Sharafinejad, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 26, No 2, 2018
  8. "Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors"
    Fatemeh Refan, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 18, No 6, pp.1-9, 2018
  9. "Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors"
    Fatemeh Refan, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 25, No 7, pp.2059-2070, 2017
  10. "SENSIBLE: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs"
    Zana Ghaderi, Mohammad Ebrahimi, Eli Bozorgzadeh, Nader Bagherzadeh, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON COMPUTERS, Vol. 66, No 5, pp.919-926, 2017
  11. "Stochastic testing of processing cores in a many-core architecture"
    Arezoo Kamran, Zainalabedin Navabi Shirazi
    INTEGRATION-THE VLSI JOURNAL, Vol. 55, No 1, pp.183-193, 2016
  12. "Self-Healing Many-Core Architecture: Analysis and Evaluation"
    Arezoo Kamran, Zainalabedin Navabi Shirazi
    VLSI Design, Vol. 2016, No 1, pp.1-17, 2016
  13. "Automatic High-level Data-flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition"
    Samaneh Ghandali, Bijan Alizadehmalafeh, ماساهیرو فوجیتا, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON COMPUTERS, Vol. 64, No 6, pp.1579-1593, 2015
  14. "System-level assertions: approach for electronic system-level verification"
    Hassan Sohofi, Zainalabedin Navabi Shirazi
    IET Computers and Digital Techniques, Vol. 9, No 3, pp.142-152, 2015
  15. "Hardware Acceleration of Online Error Detection in Many-Core Processors"
    Arezoo Kamran, Zainalabedin Navabi Shirazi
    CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, Vol. 38, No 2, pp.143-153, 2015
  16. "A Novel Modeling Approach for System-Level Application Mapping Targeted for Configurable Architecture"
    Hossein Sabaghian, Seyed Ali Shahabi, Zainalabedin Navabi Shirazi
    CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, Vol. 37, No 4, pp.192-202, 2014
  17. "A New Approach for Automatic Test Pattern Generation in Register transfer Level Circuits"
    محمد میرزائی, Mahmoud Tabandeh , Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE DESIGN & TEST OF COMPUTERS, Vol. -, No 99, 2012
  18. "TransactionLevel Formal Verification Using Timed Automata"
    Zainalabedin Navabi Shirazi, Amir Ali Ghafrani , Hamid Nouri , Fatemeh Javaheri
    Journal of Shanghai University, Vol. 39, No 5, pp.462-471, 2010
  19. "Multi Level Test Package"
    Fatemeh Javaheri , Somayeh Sadeghi , Parisa Shaafi , Zainalabedin Navabi Shirazi, Sina Mahmoudi , Atieh Lotfi , Amirali Ghofrani
    Journal of Shanghai University, Vol. -, 2010
  20. "Real Time Embedded Emotional Controller"
    Mohammad Reza Jamali , Masoud Dehyadegari , Arash Arami , Caro Lucas, Zainalabedin Navabi Shirazi
    NEURAL COMPUTING & APPLICATIONS, Vol. 19, No 1, pp.13-19, 2010
  21. "SystemAda An Ada Based System - Level Hardware Description Language"
    Negin Mahani , Parnian Mokri , Mahshid Sedghi , Zainalabedin Navabi Shirazi
    ACM SIGAda Ada Letters, Vol. 29, No 2, pp.19-15, 2009
  22. "System Level Hardware Design and Simulation with SystemAda"
    Negin Mahani , Parnian Mokri , Zainalabedin Navabi Shirazi
    ACM Press, Ada Letters, Vol. 29, No 1, pp.22-19, 2009
  23. "A Low - Power High Throughput Link Splitting Router for NoCs"
    Mohsen Saneei , Ali Afzali Kousha, Zainalabedin Navabi Shirazi
    Journal of Zhejiang University-SCIENCE A, Vol. 9, No 12, pp.1708-1714, 2008
  24. "Low Overhead DFT Using CDFG by Modifying Controller"
    Mohammad Hosseinabady , Pejman Lotfi Kamran , Fabrizio Lombardi , Zainalabedin Navabi Shirazi
    IET Computers and Digital Techniques, Vol. 4, No 1, pp.333-322, 2007
  25. "Degradable mesh-based on-chip networks using programmable routing tables"
    Ali Shahabi , Nima Honarmand , Hasan Sahafi , Zainalabedin Navabi Shirazi
    IEICE Electronics Express, Vol. 4, No 10, pp.339-332, 2007
  26. "Low Test Application Time Resource Binding for Behavioral Synthesis"
    Mohammad Hosseinabady , Pejman Lotfi Kamran , Zainalabedin Navabi Shirazi
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, Vol. 2, No 2, pp.1-22, 2007
  27. "A Test Approach for Look - Up Table Based FPGAs"
    Ehsan Atoofian , Zainalabedin Navabi Shirazi
    JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, Vol. 21, No 1, pp.141-146, 2006
  28. "Scan - Based Structure with Reduced Static and Dynamic Power Consumption"
    Shervin Sharifi , Javid Jaffari , Mohammad Hosseinabady , Ali Afzali Kousha, Zainalabedin Navabi Shirazi
    Journal of Low Power Electronics, Vol. 2, No 3, pp.477-487, 2006
  29. "Instruction - Level Test Methodology for CPU Core Self - Testing"
    Saeed Shamshiri , Hadi Esmaeilzadeh , Zainalabedin Navabi Shirazi
    ACM Transaction, Vol. 10, No 4, pp.689-678, 2005
  30. "Using RT Level Component Descriptions For Single Stuck - at Hierarchical Fault Simulation"
    Zainalabedin Navabi Shirazi, Shahrzad Mirkhani , Meisam Lavasani , Fabrizio Lombardi
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, Vol. 20, No 6, pp.589-575, 2004
  31. "Word Level Symbolic Simulation in Processor Verification"
    B Alizadeh , Zainalabedin Navabi Shirazi
    IET Computers and Digital Techniques, Vol. 151, No 5, pp.356-366, 2004
  32. "کاوش فضای طراحی سطح بالای مدلهای نوروفازی خطی محلی برای سیستم های نهفته"
    محمدرضا بهارانی، حمید نوری، محمد علی عسگری، زین العابدین نوابی شیرازی
    FUZZY SETS AND SYSTEMS، نسخه 253، صفحات:44-63، 1393
  33. "طراحی الکترونیک در سطح سیستم: زمینه های پیدایش و راهکارهای بهره برداری"
    زین العابدین نوابی شیرازی، سمیه صادقی
    آموزش مهندسی ایران، نسخه 16، شماره 62، صفحات:117-140، 1393

مقالات علمی ارائه شده در همایش‌ها

  1. "Real-Time Automotive Accident Detection Using Unsupervised Machine Learning"
    Reza Baharvand, Mahsa Jamshidi, Mozhgan Rezaie, Rezgar Sadeghi, Zainalabedin Navabi Shirazi
    EWDTS 2024, 2024
  2. "Sharing AES Engine for RISC-V Custom Instructions Performing Encryption and Decryption"
    Zahra Hojati, Zahra Jahanpeima, Maryam Rajabali Panah, Hossein Ta'ati, Atefeh Rabiei, Zainalabedin Navabi Shirazi
    EWDTS 2024, 2024
  3. "AZMA: A Zynq-based Monitoring and Fault Injection Framework for Processor Assessment"
    Zahra Mahdavi KLISHOMI, Rezgar Sadeghi, Ali Shayanpour, Amirhosein Yazdanpanah, Zainalabedin Navabi Shirazi
    EWDTS 2024, 2024
  4. "A Hierarchy of Machine Learning Processing Elements with Joint Micro programmable Computation and Indexing"
    Sepideh Kheirollahi, Sinatra Babele, Zainalabedin Navabi Shirazi
    EWDTS 2024, 2024
  5. "LBIST Configuration and Golden Signature Extraction of Black Box IP Cores"
    Fatemeh Mohammadzadeh, Zeynab Sanati, Zainalabedin Navabi Shirazi
    EWDTS 2024, 2024
  6. "Configurable DRAM Access for Neural Network Accelerators: A SystemC Virtual Platform Approach"
    Tina Hashemi, Rezgar Sadeghi, Maryam Rajabali Panah, Zahra Hojati, Zainalabedin Navabi Shirazi
    EWDTS 2024, 2024
  7. "Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation"
    Katayoon Basharkhah, Zainalabedin Navabi Shirazi
    ISVLSI 2024, 2024
  8. "Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction"
    Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad Javad Zare, Zainalabedin Navabi Shirazi
    ETS 2023, 2023
  9. "A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators"
    Nooshin Nosrati, Zainalabedin Navabi Shirazi
    DDECS 2023, 2023
  10. "A Low-Cost Combinational Approximate Multiplier"
    Zahra Hojati, Zainalabedin Navabi Shirazi
    DDECS 2023, 2023
  11. "MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors"
    Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi Shirazi
    IOLTS 2022, 2022
  12. "A Secure Canary-Based Hardware Approach Against ROP"
    Mahboube Sadghipour rousari, Ebrahim Nouri, Fatemeh Sheikhshoaei, Paolo Prinetto , Zainalabedin Navabi Shirazi
    ITASEC 2022, 2022
  13. "Resiliency to Soft-Errors for Embedded Processors Using ML-based Checkers"
    Nooshin Nosrati, Zainalabedin Navabi Shirazi, Maksim Jenihhin
    ETS 2022, 2022
  14. "Concurrent Error Detection for LSTM Accelerators"
    Nooshin Nosrati, [] [], Mahboube Sadghipour rousari, Zainalabedin Navabi Shirazi
    ETS 2022, 2022
  15. "AFTAB: A RISC-V Implementation with Configurable Gateways for Security"
    Maryam Rajabali Panah, Mahboube Sadghipour rousari, Zahra Jahanpeima, Gianluca Roascio, Paolo Prinetto, Zainalabedin Navabi Shirazi
    EWDTS 2021, 2021
  16. "n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator"
    Mahboube Sadghipour rousari, Hanieh Totonchi Asl, Zainalabedin Navabi Shirazi
    ISVLSI 2021, 2021
  17. "Integrating an Interconnect BIST with Crosstalk Avoidance Hardware"
    Mahsa Akhsham, Zainalabedin Navabi Shirazi
    IOLTS 2021, 2021
  18. "Online Testing of a Row-Stationary Convolution Accelerator"
    Mohammad Rasoul Roshanshah, Katayoon Basharkhah, Zainalabedin Navabi Shirazi
    2021 IEEE European Test Symposium (ETS), 2021
  19. "Compensating Detection Latency of FPGA Scrubbers with a Collaborative Functional Hardware Duplication"
    Mohammad Reza Naeemi Khaledi, mohammad ebrahimi, Zainalabedin Navabi Shirazi
    2021 IEEE Microelectronics Design & Test Symposium (MDTS), 2021
  20. "Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator"
    Maryam Rajabalipanah, [] [], Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi Shirazi
    IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2020
  21. "Built-In Predictors for Dynamic Crosstalk Avoidance"
    Rezgar Sadeghi, Zainalabedin Navabi Shirazi
    ETS 2020, 2020
  22. "DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation"
    Mahboobeh Sadeghipour, Mohammad Ali Saber, Zainalabedin Navabi Shirazi
    DDECS 2020, 2020
  23. "Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations"
    Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Maryam Ghasemi, Zainalabedin Navabi Shirazi
    DDECS 2020, 2020
  24. "ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links"
    Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi Shirazi
    VTS 2020, 2020
  25. "An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements"
    Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi Shirazi
    EWDTS 2019, 2019
  26. "Making System Level Test Possible bt a Mixed-mode, Multi-level, Integrated Modeling Environment"
    Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi Shirazi
    EWDTS 2019, 2019
  27. "SCOAP-based Directed Random Test Generation for Combinational Circuits"
    Seyyede Maryam Ghasemy, Maryam Rajabalipanah, Saeideh Sarmadi, Zainalabedin Navabi Shirazi
    EWDTS 2019, 2019
  28. "From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization"
    Samira Ahmadi farsani, Katayoon Basharkhah, Amin Mohaghegh, Zainalabedin Navabi Shirazi
    EWDTS 2019, 2019
  29. "An ESL Environment for Modeling Electrical Interconnect Faults"
    Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi Shirazi
    ISVLSI 2019, 2019
  30. "Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme"
    Mahsa Akhsham, Atefesadat Seyedolhosseini, Zainalabedin Navabi Shirazi
    ETS 2019, 2019
  31. "Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling"
    Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi Shirazi
    ETS 2019, 2019
  32. "Near-Optimal Node Selection Procedure for Aging Monitor Placement"
    Somayeh Sadeghi kohan, Arash Vafaei, Zainalabedin Navabi Shirazi
    IOLTS, 2018
  33. "Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture"
    Ramin Rezaeizadeh, Somayyeh Sadeghi, Zainalabedin Navabi Shirazi
    GLSIVLSI 2018, 2018
  34. "A Novel SAT-based ATPG Approach for Transition Delay Faults"
    Farzane Zokaee, Hossein Sabaghian, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi Shirazi
    IEEE International High Level Design Validation and Test Workshop (HLDVT), 2017
  35. "Reducing Search Space for Fault Diagnosis: A Probability-based Scoring Approach"
    حسین صباغیان بیدگلی , Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ISVLSI 2017, 2017
  36. "Online Profiling for Cluster-Specific Variable Rate Refreshing in High-Density DRAM Systems"
    Rasoul Sharifi, Zainalabedin Navabi Shirazi
    European Test Symposium (ETS 2017), 2017
  37. "TruncApp: A Truncation-based Approximate Divider for Energy Efficient DSP Applications"
    Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali Kousha, Massoud Pedram, Zainalabedin Navabi Shirazi
    DATE 2017, 2017
  38. "Universal Mitigation of NBTI-Induced Aging by Design Randomization"
    Maksim Jenihhin, Alexander Kamkin, Somayyeh Sadeghi, Zainalabedin Navabi Shirazi
    EWDTS 2016, 2016
  39. "ESL Design with RTL-Verified Predesigned Abstract Communication Channels"
    Hamed Najafi haghi, Mikhail Chupilko, Alexander Kamkin, Zainalabedin Navabi Shirazi
    EWDTS 2016, 2016
  40. "Early Prediction of Timing Critical Instructions in Pipeline Processor"
    Hanieh Hashemi, Arash Fouman Ajirlou, Morteza Soltani, Zainalabedin Navabi Shirazi
    Baltic Electronic Conference (BEC), 2016
  41. "Optimistic Clock Adjustment for preventing Better-Than-Worst-Case Violations"
    Seyedeh Hanieh Hashemi, Zainalabedin Navabi Shirazi
    VLSI SoC 2016, 2016
  42. "Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping"
    Morteza Soltani, Mohammad Ebrahimi, Zainalabedin Navabi Shirazi
    GLSIVLSI 2016, 2016
  43. "Path Selection and Sensor Insertion Flow for Age Monitoring in FPGAs"
    Mohammad Ebrahimi, Zana Ghaderi, Eli Bozorgzadeh, Zainalabedin Navabi Shirazi
    Design, Automation & Test in Europe (DATE 2016), 2016
  44. "Signature Oriented Model Pruning to Facilitate Multi-Threaded Processors Debugging"
    Fatemeh Refan, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE VLSI Test Symposium (VTS 2015), 2015
  45. "Application-Specific Power-Aware Mapping for Reconfigurable NoC Architectures"
    Mehran Goli, Amin Ghasemazar, Zainalabedin Navabi Shirazi
    Design and Technology of Integrated Systems (DTIS2015), 2015
  46. "Utilizing NOPs for Online Deterministic Testing of Simple Processing Cores"
    Rasoul Jafari, Elham Zahraei Salehi, Zainalabedin Navabi Shirazi
    Design and Technology of Integrated Systems (DTIS2015), 2015
  47. "Multi-Valued Logic Test Access Mechanism for Test Time and Power Reduction"
    Amir Reza Nekouei, Zainalabedin Navabi Shirazi
    Design and Technology of Integrated Systems (DTIS2015), 2015
  48. "Online Self Adjusting Progressive Age Monitoring of Timing Variations"
    Somayeh Sadeghi, Mehdi Kamal, John Mcneil, Paolo Prinetto, Zainalabedin Navabi Shirazi
    Design and Technology of Integrated Systems (DTIS2015), 2015
  49. "Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation"
    Somayeh Sadeghi, Arezoo Kamran, Farnaz Forooghifar, Zainalabedin Navabi Shirazi
    Design and Technology of Integrated Systems (DTIS2015), 2015
  50. "Power-Aware Online Testing of Manycore Systems in the Dark Silicon Era"
    Mohammad Hashem Haghbayan, Amir Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi Shirazi, Hannu Tenhunen
    Design Automation & Test in Europe (DATE 2015), 2015
  51. "Low Power Scheduling in High-level Synthesis using Dual-Vth Library"
    Samaneh Ghandali, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ISQED 2015, 2015
  52. "Preemptive Multi-bit IJTAG Testing with Reconfigurable Infrastructure"
    Shahrzad Keshavarz, Amir Reza Nekouei, Zainalabedin Navabi Shirazi
    DFT 2014, 2014
  53. "A Heuristic Path Selection Method For Small Delay Defects Test"
    پانیذ فروتن, مهدی کمال, Zainalabedin Navabi Shirazi
    DFT 2014, 2014
  54. "Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits"
    Farimah Farahmandi, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ISVLSI 2014, 2014
  55. "Back-annotation of Gate-level Power Properties into System Level Description"
    Najmeh Farajipour, Zainalabedin Navabi Shirazi
    NEWCAS 2014, 2014
  56. "An Off-line MDSI Interconnect BIST Incorporated in BS 1149.1"
    Marziyeh Mohammadi, Somayeh Sadeghi, Nasser Masoumi, Zainalabedin Navabi Shirazi
    ETS 2014 (European Test Symposium), 2014
  57. "Automatic Correction of Certain Design Errors Using Mutation Technique"
    Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ETS 2014 (European Test Symposium), 2014
  58. "Homogeneous Many-core Processor System Test Distribution and Execution Mechanism"
    Arezoo Kamran, Zainalabedin Navabi Shirazi
    ETS 2014 (European Test Symposium), 2014
  59. "Improving Polynomial Datapath Debugging with HEDs"
    Somayeh Sadeghi, Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi, Masahiro Fujita
    ETS 2014 (European Test Symposium), 2014
  60. "RTL Datapath Optimization using System-level Transformations"
    Samaneh Ghandali, Bijan Alizadehmalafeh, Masahiro Fujita, Zainalabedin Navabi Shirazi
    ISQED, 2014
  61. "RTL Datapath Optimization Using System Level Transformations"
    Samaneh Ghandali, Bijan Alizadehmalafeh, Masahiro Fujita, Zainalabedin Navabi Shirazi
    ISQED, 2014
  62. "Assertion-Based Verification for System-Level Designs"
    Hassan Sohofi, Zainalabedin Navabi Shirazi
    ISQED, 2014
  63. "Configurable Systolic Matrix Multiplication"
    پرستو کامران فر, Seyed Ali Shahabi, غزاله واژبخت, Zainalabedin Navabi Shirazi
    VLSI Design, 2014
  64. "Online Periodic Test Mechanism for Homogeneous Many-core Processors"
    Arezoo Kamran, Zainalabedin Navabi Shirazi
    International Conference on Very Large Scale Integration (VLSI-SoC 2013), 2013
  65. "A Probabilistic Approach for Counterexample Generation to Aid Design Debugging"
    Payman Behnam, Hossein Sabaghian, Bijan Alizadehmalafeh, Kamyar Mohajerani, Zainalabedin Navabi Shirazi
    EWDTS 2013, 2013
  66. "Mutation-based Technique for Automatic Correction of Functional Bugs in Digital Designs"
    Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    International Symposium on VLSI, 2013
  67. "Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits"
    Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    International Symposium VLSI, 2013
  68. "A Probabilistic and Constraint Based Approach for Low Power Test Generation"
    حسین صباغیان بیدگلی, مجید نمکی شوشتری, Zainalabedin Navabi Shirazi
    Asian Test Symposium 2012, 2012
  69. "Mutation Based Debugging Technique with Auto-Correction Mechanism for RTL Designs"
    Bijan Alizadehmalafeh, پیمان بهنام, Zainalabedin Navabi Shirazi, ماساهیرو فوجیتا
    IEEE International Workshop on Silicon Debug and Diagnosis, 2012
  70. "BS 1149.1 Extensions for an Online Interconnect Fault Detection and Recovery"
    سمیه صادقی کهن, مجید نمکی شوشتری, فاطمه جواهری, Zainalabedin Navabi Shirazi
    ITC 2012, 2012
  71. "Polynomial Datapath Synthesis and Optimization Based on Vanishing Polynomial over Z(2m and Algebraic Techniques"
    Bijan Alizadehmalafeh, سمانه قندالی, Zainalabedin Navabi Shirazi, ماساهیرو فوجیتا
    International Conference on Formal Methods and Models for Co-design, 2012
  72. "An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture"
    الهه صدرالدینی, غلامرضا رحیمی, پانیذ فروتن, محمود فتحی, Zainalabedin Navabi Shirazi
    EWDTS 2012, 2012
  73. "Extracting Complete Set of Equations to Analyze VHDL-AMS Descriptions"
    آرزو کامران, وحید جانفزا, Zainalabedin Navabi Shirazi
    EWDTS 2012, 2012
  74. "A New Structure for Interconnect Offline Testing"
    سمیه صادقی کهن, شهرزاد کشاورز, فرزانه ذکایی, فریماه فرهمندی, Zainalabedin Navabi Shirazi
    EWDTS 2012, 2012
  75. "Optimization Consideration in QCA Designs"
    زهرا نجفی حقی, مرضیه محمدی, Behjat Forouzandeh, Zainalabedin Navabi Shirazi
    EWDTS 2012, 2012
  76. "Taking Electronic Design from RTL to ESL"
    Zainalabedin Navabi Shirazi, فاطمه جواهری
    European Workshop on Microelectronics Education, 2012
  77. "HDLs from Test Education Perspective"
    Zainalabedin Navabi Shirazi, Ghazal Nemati
    European Workshop on Microelectronics Education, 2012
  78. "Power Constraint Testing for Multi-Clock Domain SoCs Using Concurrent Hybrid BIST"
    محمد هاشم حق بیان, Saeed Safari, Zainalabedin Navabi Shirazi
    DDECS 2012, 2012
  79. "Effective RT-Level Software-Based Self-Testing of Embedded Processor Cores"
    Zainalabedin Navabi Shirazi, Sara Kabiri
    DDECS 2012, 2012
  80. "Near Optimal Machine Learning Based Random Test Generation"
    نیکی شاکری, نسترن نعمتی, Majid Nili Ahmad Abadi, Zainalabedin Navabi Shirazi
    EWDTS10, 2010
  81. "Low cost Error Tolerant Motion Estimation for H.264/AVC Standard"
    Mohammad Hossin Sargolzaie, Mehdi Semsarzadeh, Mahmoud Reza Hashemi, Zainalabedin Navabi Shirazi
    East-West Design & Test Symposium (EWDTS 2009), 2009
  82. "Optimized Assignment Coverage Computation in Formal Verification of Digital Systems"
    Majid Nabi, Hamid Shojaei, Siamak Mohammadi, Zainalabedin Navabi Shirazi
    Asian Test Symposium 2007, 2007
  83. "Assignment Coverage, A Complementary Coverage Metric in Formal Verification"
    Majid Nabi, Hamid Shojaei, Siamak Mohammadi, Zainalabedin Navabi Shirazi
    Design & Technology of Intgrated Systems (DTIS '07), 2007
  84. "Improved Assertion Lifetime via Assertion Based Testing Methodology"
    Mohammad Riazati, Siamak Mohammadi, Ali Afzali Kousha, Zainalabedin Navabi Shirazi
    18th International Conference on Microelectronics, ICM 2006, 2006
  85. "Assertion Efficiency Assessment Method"
    Mohammad Riazati, Siamak Mohammadi, Zainalabedin Navabi Shirazi
    7th Workshop on RTL and High Level Testing, WRTLT'06, 2006
  86. "Non-overlapping Set of Efficient Assertions"
    Mohammad Riazati, Siamak Mohammadi, Zainalabedin Navabi Shirazi
    Norchip Conference, 2006