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Zainalabedin Navabi Shirazi

Professor

Update: 2024-11-21

Zainalabedin Navabi Shirazi

College of Engineering / Electrical and Computer ENG

Journal Paper

  1. "Pico-Programmable Neurons to Reduce Computations for Deep Neural Network Accelerators"
    Alireza Nahvi, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 32, No 7, pp.1-12, 2024
  2. "Analysis and Enhancement of Resilience for LSTM Accelerators Using Residue-Based CEDs"
    Nooshin Nosrati, Zainalabedin Navabi Shirazi
    IEEE Access, Vol. 12, pp.52851-52866, 2024
  3. "An Efficient RTL Design for a Wearable Brain–Computer Interface"
    Tahereh Vasei, Mohammad Ali Saber, Alireza Nahvy, Zainalabedin Navabi Shirazi
    IET Computers and Digital Techniques, Vol. 2024, pp.1-15, 2024
  4. "LUT Input Reordering to Reduce Aging Impact on FPGA LUTs"
    Mohammad Ebrahimi, Rezgar Sadeghi, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON COMPUTERS, Vol. 69, No 10, pp.1500-1506, 2020
  5. "Selecting Representative Critical Paths for Sensor Placement Provides Early FPGA Aging Information"
    Mohammad Ebrahimi, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 39, No 10, 2020
  6. "Self-Adjusting Monitor for Measuring Aging Rate and Advancement"
    Somayeh Sadeghi Kohan, Mehdi Kamal, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON EMERGING TOPICS IN COMPUTING, Vol. 8, No 3, 2020
  7. "Automatic Correction of Dynamic Power Management Architecture in Modern Processors"
    Reza Sharafinejad, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 26, No 2, 2018
  8. "Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors"
    Fatemeh Refan, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, Vol. 25, No 7, pp.2059-2070, 2017
  9. "SENSIBLE: A Highly Scalable SENsor DeSIgn for Path-Based Age Monitoring in FPGAs"
    Zana Ghaderi, Mohammad Ebrahimi, Eli Bozorgzadeh, Nader Bagherzadeh, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON COMPUTERS, Vol. 66, No 5, pp.919-926, 2017
  10. "Stochastic testing of processing cores in a many-core architecture"
    Arezoo Kamran, Zainalabedin Navabi Shirazi
    INTEGRATION-THE VLSI JOURNAL, Vol. 55, No 1, pp.183-193, 2016
  11. "Self-Healing Many-Core Architecture: Analysis and Evaluation"
    Arezoo Kamran, Zainalabedin Navabi Shirazi
    VLSI Design, Vol. 2016, No 1, pp.1-17, 2016
  12. "Automatic High-level Data-flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition"
    Samaneh Ghandali, Bijan Alizadehmalafeh, ماساهیرو فوجیتا, Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON COMPUTERS, Vol. 64, No 6, pp.1579-1593, 2015
  13. "System-level assertions: approach for electronic system-level verification"
    Hassan Sohofi, Zainalabedin Navabi Shirazi
    IET Computers and Digital Techniques, Vol. 9, No 3, pp.142-152, 2015
  14. "Hardware Acceleration of Online Error Detection in Many-Core Processors"
    Arezoo Kamran, Zainalabedin Navabi Shirazi
    CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, Vol. 38, No 2, pp.143-153, 2015
  15. "A Novel Modeling Approach for System-Level Application Mapping Targeted for Configurable Architecture"
    Hossein Sabaghian, Seyed Ali Shahabi, Zainalabedin Navabi Shirazi
    CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, Vol. 37, No 4, pp.192-202, 2014
  16. "A New Approach for Automatic Test Pattern Generation in Register Transfer Level Circuits"
    محمد میرزائی, محمود تابنده, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE DESIGN & TEST OF COMPUTERS, Vol. 30, No 4, pp.49-59, 2013
  17. "Low Overhead DFT Using CDFG by Modifying Controller"
    Mohammad Hosseinabady , Pejman Lotfi Kamran , Fabrizio Lombardi , Zainalabedin Navabi Shirazi
    IET Computers and Digital Techniques, Vol. 4, No 1, pp.333-322, 2007
  18. "Degradable mesh-based on-chip networks using programmable routing tables"
    Ali Shahabi , Nima Honarmand , Hasan Sahafi , Zainalabedin Navabi Shirazi
    IEICE Electronics Express, Vol. 4, No 10, pp.339-332, 2007
  19. "Low Test Application Time Resource Binding for Behavioral Synthesis"
    Mohammad Hosseinabady , Pejman Lotfi Kamran , Zainalabedin Navabi Shirazi
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, Vol. 2, No 2, pp.1-22, 2007
  20. "A Test Approach for Look - Up Table Based FPGAs"
    Ehsan Atoofian , Zainalabedin Navabi Shirazi
    JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, Vol. 21, No 1, pp.141-146, 2006
  21. "Scan - Based Structure with Reduced Static and Dynamic Power Consumption"
    Shervin Sharifi , Javid Jaffari , Mohammad Hosseinabady , Ali Afzali Kousha, Zainalabedin Navabi Shirazi
    Journal of Low Power Electronics, Vol. 2, No 3, pp.477-487, 2006
  22. "Instruction - Level Test Methodology for CPU Core Self - Testing"
    Saeed Shamshiri , Hadi Esmaeilzadeh , Zainalabedin Navabi Shirazi
    ACM Transaction, Vol. 10, No 4, pp.689-678, 2005
  23. "Using RT Level Component Descriptions For Single Stuck - at Hierarchical Fault Simulation"
    Zainalabedin Navabi Shirazi, Shahrzad Mirkhani , Meisam Lavasani , Fabrizio Lombardi
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, Vol. 20, No 6, pp.589-575, 2004
  24. "Word Level Symbolic Simulation in Processor Verification"
    B Alizadeh , Zainalabedin Navabi Shirazi
    IET Computers and Digital Techniques, Vol. 151, No 5, pp.356-366, 2004
  25. "A Transistor Level Link for VHDL Simulation of VLSI Circuits"
    Zainalabedin Navabi Shirazi
    SIMULATION-TRANSACTIONS OF THE SOCIETY FOR MODELING AND SIMULATION INTERNATIONAL, Vol. 64, 1995
  26. "A High Level Language For Design and Modeling of Hardware"
    Zainalabedin Navabi Shirazi
    Journal of Systems and Software, Vol. -, No 9, 1992
  27. "HDL Front End for a Cell Based Silicon Compiler"
    Zainalabedin Navabi Shirazi, Kia Doroudi
    International Journal of Gaming and Computer-Mediated Simulations, Vol. -, 1992
  28. "Compiling Gate RC Models Into a Top Level Simulation Model for Rough Timing Analysis of VLSI Circuits"
    Zainalabedin Navabi Shirazi
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 15, No 6, pp.313-320, 1991
  29. "Synthesis of VLSI Circuits From Behavioral Descriptions"
    Zainalabedin Navabi Shirazi, John Spillane
    MICROELECTRONICS JOURNAL, Vol. 22, No 6, pp.13-1, 1991
  30. "Faculty Profile Zainalabedin Navabi of N.U.Speaks Language of Computers"
    Zainalabedin Navabi Shirazi
    Micro News Publication of Massachusetts Microelectronics center, Vol. 4, No 2, 1990
  31. "Compiling an RT Level Hardware Description Language into Layout of NMOS Cells"
    Zainalabedin Navabi Shirazi, Kia Doroudi
    Microprocessing and Microprogramming, Vol. 18, pp.123-129, 1986
  32. "Generating Gate Level Two Phase Dynamic MOS Logic From AHPL"
    Zainalabedin Navabi Shirazi
    Microprocessing and Microprogramming, Vol. 16, pp.89-94, 1985
  33. "Hardware Compilation from an RTL to a Storage Logic Array Target"
    Zainalabedin Navabi Shirazi, F J Hill , C H Chiang , Duan Ping Chen , M Masud
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, Vol. 3, No 3, pp.208-217, 1984
  34. "Structure Specification with a Procedural Hardware Desription Language"
    Hill F J , Swanson R E , Masud M , Zainalabedin Navabi Shirazi
    IEEE TRANSACTIONS ON COMPUTERS, Vol. C-30, No 2, pp.157-161, 1981
  35. "Digitizing for Computer-Aided Finite Element Model Generation—Part 1: The General Program"
    Zainalabedin Navabi Shirazi
    Journal of Mechanical Design - Transactions of the ASME, Vol. -, No 29403, pp.105-552, 1980
  36. "Digitizing for Computer-Aided Finite Element Model Generation - Part 2. Use of Digitizing in Mesh Generation"
    Zainalabedin Navabi Shirazi
    Journal of Mechanical Design - Transactions of the ASME, Vol. -, pp.102-560, 1980
  37. "High-level design space exploration of locally linear neuro-fuzzy models foe embedded systems"
    Mohammadreza Baharani, Hamid Noori, Mohammad Aliasgari, Zainalabedin Navabi Shirazi
    FUZZY SETS AND SYSTEMS, Vol. 253, pp.44-63, 2014
  38. "System Level Design: facilitations and Utilizations"
    Zainalabedin Navabi Shirazi, Somayeh Sadeghi
    Iranian Journal of Engineering Education, Vol. 16, No 62, pp.117-140, 2014

Conference Paper

  1. "Event-Based Power Analysis Integrated with Timing Characterization and Logic Simulation"
    Katayoon Basharkhah, Zainalabedin Navabi Shirazi
    ISVLSI 2024, 2024
  2. "Learning Electrical Behavior of Core Interconnects for System-Level Crosstalk Prediction"
    Katayoon Basharkhah, Raheleh Sadat Mirhashemi, Nooshin Nosrati, Mohammad Javad Zare, Zainalabedin Navabi Shirazi
    ETS 2023, 2023
  3. "A Low-Cost Combinational Approximate Multiplier"
    Zahra Hojati, Zainalabedin Navabi Shirazi
    DDECS 2023, 2023
  4. "A Low-cost Residue-based Scheme for Error-resiliency of RNN Accelerators"
    Nooshin Nosrati, Zainalabedin Navabi Shirazi
    DDECS 2023, 2023
  5. "MLC: A Machine Learning Based Checker For Soft Error Detection In Embedded Processors"
    Nooshin Nosrati, Maksim Jenihhin, Zainalabedin Navabi Shirazi
    IOLTS 2022, 2022
  6. "A Secure Canary-Based Hardware Approach Against ROP"
    Mahboube Sadghipour rousari, Ebrahim Nouri, Fatemeh Sheikhshoaei, Paolo Prinetto , Zainalabedin Navabi Shirazi
    ITASEC 2022, 2022
  7. "Concurrent Error Detection for LSTM Accelerators"
    Nooshin Nosrati, [] [], Mahboube Sadghipour rousari, Zainalabedin Navabi Shirazi
    ETS 2022, 2022
  8. "Resiliency to Soft-Errors for Embedded Processors Using ML-based Checkers"
    Nooshin Nosrati, Zainalabedin Navabi Shirazi, Maksim Jenihhin
    ETS 2022, 2022
  9. "AFTAB: A RISC-V Implementation with Configurable Gateways for Security"
    Maryam Rajabali Panah, Mahboube Sadghipour rousari, Zahra Jahanpeima, Gianluca Roascio, Paolo Prinetto, Zainalabedin Navabi Shirazi
    EWDTS 2021, 2021
  10. "n-DiCE-LSTM: An n-Dimensional Configurable and Efficient Architecture for LSTM Accelerator"
    Mahboube Sadghipour rousari, Hanieh Totonchi Asl, Zainalabedin Navabi Shirazi
    ISVLSI 2021, 2021
  11. "Testing a RISCV-Like Architecture With an HDL-Based Virtual Tester"
    Nooshin Nosrati, Katayoon Basharkhah, Hanieh Totonchi Asl, Zahra Mahdavi, Zainalabedin Navabi Shirazi
    2021 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 2021
  12. "Integrating an Interconnect BIST with Crosstalk Avoidance Hardware"
    Mahsa Akhsham, Zainalabedin Navabi Shirazi
    IOLTS 2021, 2021
  13. "Online Testing of a Row-Stationary Convolution Accelerator"
    Mohammad Rasoul Roshanshah, Katayoon Basharkhah, Zainalabedin Navabi Shirazi
    2021 IEEE European Test Symposium (ETS), 2021
  14. "Compensating Detection Latency of FPGA Scrubbers with a Collaborative Functional Hardware Duplication"
    Mohammad Reza Naeemi Khaledi, mohammad ebrahimi, Zainalabedin Navabi Shirazi
    2021 IEEE Microelectronics Design & Test Symposium (MDTS), 2021
  15. "Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator"
    Maryam Rajabalipanah, [] [], Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Zainalabedin Navabi Shirazi
    IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2020
  16. "Built-In Predictors for Dynamic Crosstalk Avoidance"
    Rezgar Sadeghi, Zainalabedin Navabi Shirazi
    ETS 2020, 2020
  17. "Reconfiguration of Embedded Accelerators by Microprogramming for Intensive Loop Computations"
    Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Maryam Rajabalipanah, Maryam Ghasemi, Zainalabedin Navabi Shirazi
    DDECS 2020, 2020
  18. "DiBA: n-Dimensional Bitslice Architecture for LSTM Implementation"
    Mahboobeh Sadeghipour, Mohammad Ali Saber, Zainalabedin Navabi Shirazi
    DDECS 2020, 2020
  19. "ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links"
    Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi Shirazi
    VTS 2020, 2020
  20. "Making System Level Test Possible bt a Mixed-mode, Multi-level, Integrated Modeling Environment"
    Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi Shirazi
    EWDTS 2019, 2019
  21. "From Abstract Modeling of ADAS Applications to an Accelerator-based Hardware Realization"
    Samira Ahmadi farsani, Katayoon Basharkhah, Amin Mohaghegh, Zainalabedin Navabi Shirazi
    EWDTS 2019, 2019
  22. "An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements"
    Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi Shirazi
    EWDTS 2019, 2019
  23. "SCOAP-based Directed Random Test Generation for Combinational Circuits"
    Seyyede Maryam Ghasemy, Maryam Rajabalipanah, Saeideh Sarmadi, Zainalabedin Navabi Shirazi
    EWDTS 2019, 2019
  24. "An ESL Environment for Modeling Electrical Interconnect Faults"
    Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi Shirazi
    ISVLSI 2019, 2019
  25. "Test Adapted Shielding by a Multipurpose Crosstalk Avoidance Scheme"
    Mahsa Akhsham, Atefesadat Seyedolhosseini, Zainalabedin Navabi Shirazi
    ETS 2019, 2019
  26. "Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling"
    Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi Shirazi
    ETS 2019, 2019
  27. "Near-Optimal Node Selection Procedure for Aging Monitor Placement"
    Somayeh Sadeghi kohan, Arash Vafaei, Zainalabedin Navabi Shirazi
    IOLTS, 2018
  28. "Performance and Energy Enhancement through an Online Single/Multi Level Mode Switching Cache Architecture"
    Ramin Rezaeizadeh, Somayyeh Sadeghi, Zainalabedin Navabi Shirazi
    GLSIVLSI 2018, 2018
  29. "A Novel SAT-based ATPG Approach for Transition Delay Faults"
    Farzane Zokaee, Hossein Sabaghian, Vahid Janfaza, Payman Behnam, Zainalabedin Navabi Shirazi
    IEEE International High Level Design Validation and Test Workshop (HLDVT), 2017
  30. "Reducing Search Space for Fault Diagnosis: A Probability-based Scoring Approach"
    حسین صباغیان بیدگلی , Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ISVLSI 2017, 2017
  31. "Online Profiling for Cluster-Specific Variable Rate Refreshing in High-Density DRAM Systems"
    Rasoul Sharifi, Zainalabedin Navabi Shirazi
    European Test Symposium (ETS 2017), 2017
  32. "TruncApp: A Truncation-based Approximate Divider for Energy Efficient DSP Applications"
    Shaghayegh Vahdat, Mehdi Kamal, Ali Afzali Kousha, Massoud Pedram, Zainalabedin Navabi Shirazi
    DATE 2017, 2017
  33. "Universal Mitigation of NBTI-Induced Aging by Design Randomization"
    Maksim Jenihhin, Alexander Kamkin, Somayyeh Sadeghi, Zainalabedin Navabi Shirazi
    EWDTS 2016, 2016
  34. "ESL Design with RTL-Verified Predesigned Abstract Communication Channels"
    Hamed Najafi haghi, Mikhail Chupilko, Alexander Kamkin, Zainalabedin Navabi Shirazi
    EWDTS 2016, 2016
  35. "Early Prediction of Timing Critical Instructions in Pipeline Processor"
    Hanieh Hashemi, Arash Fouman Ajirlou, Morteza Soltani, Zainalabedin Navabi Shirazi
    Baltic Electronic Conference (BEC), 2016
  36. "Optimistic Clock Adjustment for preventing Better-Than-Worst-Case Violations"
    Seyedeh Hanieh Hashemi, Zainalabedin Navabi Shirazi
    VLSI SoC 2016, 2016
  37. "Prolonging Lifetime of Non-volatile Last Level Caches with Cluster Mapping"
    Morteza Soltani, Mohammad Ebrahimi, Zainalabedin Navabi Shirazi
    GLSIVLSI 2016, 2016
  38. "Path Selection and Sensor Insertion Flow for Age Monitoring in FPGAs"
    Mohammad Ebrahimi, Zana Ghaderi, Eli Bozorgzadeh, Zainalabedin Navabi Shirazi
    Design, Automation & Test in Europe (DATE 2016), 2016
  39. "Signature Oriented Model Pruning to Facilitate Multi-Threaded Processors Debugging"
    Fatemeh Refan, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    IEEE VLSI Test Symposium (VTS 2015), 2015
  40. "Aging in Digital Circuits and Age Monitoring: Object-Oriented Modeling and Evaluation"
    Somayeh Sadeghi, Arezoo Kamran, Farnaz Forooghifar, Zainalabedin Navabi Shirazi
    Design and Technology of Integrated Systems (DTIS2015), 2015
  41. "Utilizing NOPs for Online Deterministic Testing of Simple Processing Cores"
    Rasoul Jafari, Elham Zahraei Salehi, Zainalabedin Navabi Shirazi
    Design and Technology of Integrated Systems (DTIS2015), 2015
  42. "Multi-Valued Logic Test Access Mechanism for Test Time and Power Reduction"
    Amir Reza Nekouei, Zainalabedin Navabi Shirazi
    Design and Technology of Integrated Systems (DTIS2015), 2015
  43. "Application-Specific Power-Aware Mapping for Reconfigurable NoC Architectures"
    Mehran Goli, Amin Ghasemazar, Zainalabedin Navabi Shirazi
    Design and Technology of Integrated Systems (DTIS2015), 2015
  44. "Online Self Adjusting Progressive Age Monitoring of Timing Variations"
    Somayeh Sadeghi, Mehdi Kamal, John Mcneil, Paolo Prinetto, Zainalabedin Navabi Shirazi
    Design and Technology of Integrated Systems (DTIS2015), 2015
  45. "Power-Aware Online Testing of Manycore Systems in the Dark Silicon Era"
    Mohammad Hashem Haghbayan, Amir Mohammad Rahmani, Mohammad Fattah, Pasi Liljeberg, Juha Plosila, Zainalabedin Navabi Shirazi, Hannu Tenhunen
    Design Automation & Test in Europe (DATE 2015), 2015
  46. "Low Power Scheduling in High-level Synthesis using Dual-Vth Library"
    Samaneh Ghandali, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ISQED 2015, 2015
  47. "A Heuristic Path Selection Method For Small Delay Defects Test"
    پانیذ فروتن, مهدی کمال, Zainalabedin Navabi Shirazi
    DFT 2014, 2014
  48. "Preemptive Multi-bit IJTAG Testing with Reconfigurable Infrastructure"
    Shahrzad Keshavarz, Amir Reza Nekouei, Zainalabedin Navabi Shirazi
    DFT 2014, 2014
  49. "Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits"
    Farimah Farahmandi, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ISVLSI 2014, 2014
  50. "Back-annotation of Gate-level Power Properties into System Level Description"
    Najmeh Farajipour, Zainalabedin Navabi Shirazi
    NEWCAS 2014, 2014
  51. "Homogeneous Many-core Processor System Test Distribution and Execution Mechanism"
    Arezoo Kamran, Zainalabedin Navabi Shirazi
    ETS 2014 (European Test Symposium), 2014
  52. "Improving Polynomial Datapath Debugging with HEDs"
    Somayeh Sadeghi, Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi, Masahiro Fujita
    ETS 2014 (European Test Symposium), 2014
  53. "Automatic Correction of Certain Design Errors Using Mutation Technique"
    Payman Behnam, Bijan Alizadehmalafeh, Zainalabedin Navabi Shirazi
    ETS 2014 (European Test Symposium), 2014
  54. "An Off-line MDSI Interconnect BIST Incorporated in BS 1149.1"
    Marziyeh Mohammadi, Somayeh Sadeghi, Nasser Masoumi, Zainalabedin Navabi Shirazi
    ETS 2014 (European Test Symposium), 2014
  55. "Assertion-Based Verification for System-Level Designs"
    Hassan Sohofi, Zainalabedin Navabi Shirazi
    ISQED, 2014
  56. "Configurable Systolic Matrix Multiplication"
    پرستو کامران فر, Seyed Ali Shahabi, غزاله واژبخت, Zainalabedin Navabi Shirazi
    VLSI Design, 2014
  57. "Online Periodic Test Mechanism for Homogeneous Many-core Processors"
    Arezoo Kamran, Zainalabedin Navabi Shirazi
    International Conference on Very Large Scale Integration (VLSI-SoC 2013), 2013
  58. "A Probabilistic Approach for Counterexample Generation to Aid Design Debugging"
    Payman Behnam, Hossein Sabaghian, Bijan Alizadehmalafeh, Kamyar Mohajerani, Zainalabedin Navabi Shirazi
    EWDTS 2013, 2013
  59. "An Online Method for Serial Interconnects Testing"
    سمیه صادقی کهن, شهرزاد کشاورز, Zainalabedin Navabi Shirazi
    WRTLT 2012, 2012
  60. "BS 1149.1 Extensions for an Online Interconnect Fault Detection and Recovery"
    سمیه صادقی کهن, مجید نمکی شوشتری, فاطمه جواهری, Zainalabedin Navabi Shirazi
    ITC 2012, 2012
  61. "A New Structure for Interconnect Offline Testing"
    سمیه صادقی کهن, شهرزاد کشاورز, فرزانه ذکایی, فریماه فرهمندی, Zainalabedin Navabi Shirazi
    EWDTS 2012, 2012
  62. "An Improved Scheme for Pre-computed Patterns in Core-based SoC Architecture"
    الهه صدرالدینی, غلامرضا رحیمی, پانیذ فروتن, محمود فتحی, Zainalabedin Navabi Shirazi
    EWDTS 2012, 2012
  63. "Extracting Complete Set of Equations to Analyze VHDL-AMS Descriptions"
    آرزو کامران, وحید جانفزا, Zainalabedin Navabi Shirazi
    EWDTS 2012, 2012
  64. "Optimization Considerations in QCA Designs"
    زهرا نجفی حقی, مرضیه محمدی, Behjat Forouzandeh, Zainalabedin Navabi Shirazi
    EWDTS 2012, 2012
  65. "Optimized Assignment Coverage Computation in Formal Verification of Digital Systems"
    Majid Nabi, Hamid Shojaei, Siamak Mohammadi, Zainalabedin Navabi Shirazi
    Asian Test Symposium 2007, 2007
  66. "Assignment Coverage, A Complementary Coverage Metric in Formal Verification"
    Majid Nabi, Hamid Shojaei, Siamak Mohammadi, Zainalabedin Navabi Shirazi
    Design & Technology of Intgrated Systems (DTIS '07), 2007
  67. "Improved Assertion Lifetime via Assertion Based Testing Methodology"
    Mohammad Riazati, Siamak Mohammadi, Ali Afzali Kousha, Zainalabedin Navabi Shirazi
    18th International Conference on Microelectronics, ICM 2006, 2006
  68. "Assertion Efficiency Assessment Method"
    Mohammad Riazati, Siamak Mohammadi, Zainalabedin Navabi Shirazi
    7th Workshop on RTL and High Level Testing, WRTLT'06, 2006
  69. "Non-overlapping Set of Efficient Assertions"
    Mohammad Riazati, Siamak Mohammadi, Zainalabedin Navabi Shirazi
    Norchip Conference, 2006